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公开(公告)号:US20190181881A1
公开(公告)日:2019-06-13
申请号:US16115237
申请日:2018-08-28
发明人: Takuya MATSUO , Atsushi MATSUMURA
CPC分类号: H03M7/40 , G06F9/3806 , G06F12/0246 , H03M7/3075 , H03M7/42 , H03M7/607 , H04N19/61
摘要: A data processing apparatus for compressing physical address values correlated to logical address values includes a first prediction unit that calculates a first predicted address value for a first input address value in input data to be compressed, a determination unit that selects an encoding processing for the first input address value according to the first predicted address value, and a compression unit configured to encode the first input address value according to the encoding processing selected by the determination unit.
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公开(公告)号:US20180276072A1
公开(公告)日:2018-09-27
申请号:US15703454
申请日:2017-09-13
发明人: Tomoya KODAMA , Takayuki ITOH , Atsushi MATSUMURA , Takuya MATSUO
CPC分类号: G06F11/1068 , G06F11/1016 , G06F11/1072 , G11C11/5671 , G11C16/04 , G11C16/0466 , G11C16/0483 , G11C16/26 , G11C2211/563
摘要: According to one embodiment, a memory controller includes one or more processors configured to function as a writing unit and a reading unit. The writing unit writes data as threshold voltages of individual memory cells. The reading unit reads the written data by detecting threshold voltages of the individual memory cells. The reading unit includes a selecting unit, a detecting unit, and an estimating unit. The selecting unit selects a read-target memory cell. The detecting unit detects a first threshold voltage at a time of reading of the read-target memory cell, and a second threshold voltage at a time of reading of at least one of adjacent memory cells that are adjacent to the read-target memory cell. The estimating unit estimates a third threshold voltage as a threshold voltage at a time of writing in the read-target memory cell based on the first threshold voltage and the second threshold voltage.
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