公开(公告)号：US20200089838A1

公开(公告)日：2020-03-19

申请号：US16288112

申请日：2019-02-28

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Kazuhiro NOJIMA ,  Tomohide TEZUKA ,  Atsushi ONISHI ,  Kazuhiro YAMADA ,  Shigeki NOJIMA ,  Akira HAMAGUCHI

IPC: G06F17/50 ,  G01N21/956 ,  G06T7/00 ,  G01N21/88

Abstract: An apparatus for inspecting a defect includes a memory storage and a processing unit coupled to the memory storage. The processing unit is configured to acquire pattern data for one or more patterns implemented on a wafer from a storage device, clip a portion that corresponds to the pattern data from a figure indicated by design data to generate design information and one or more circuit patterns, assign a first set of numbers to the one or more patterns of the pattern data, assign a second set of numbers to the one or more circuit patterns of the design information, generate relation information indicative of one or more correspondences between the first set of numbers and the second set of numbers, verify whether or not the one or more patterns indicated by the pattern data constitute a crucial defect based on the relation information, and send a verification result to a device.