公开(公告)号：US20210313350A1

公开(公告)日：2021-10-07

申请号：US17350161

申请日：2021-06-17

Applicant: Toshiba Memory Corporation

Inventor： Kazuhiro NOJIMA ,  Kojiro SHIMIZU

IPC: H01L27/11582 ,  H01L27/11573 ,  H01L27/1157 ,  G11C5/06

Abstract: A semiconductor storage device includes a logic circuit formed on a substrate, a first area formed on the logic circuit and has a plurality of first insulating layers and a plurality of conductive layers alternately stacked in a first direction, a plurality of memory pillars MP which extend in the first area in the first direction, a second area which is formed on the logic circuit and has the plurality of first insulating layers 33 and a plurality of second insulating layers alternately stacked in the first direction, and a contact plug CP1 which extends in the second area in the first direction and is connected to the logic circuit.

公开(公告)号：US20200089838A1

公开(公告)日：2020-03-19

申请号：US16288112

申请日：2019-02-28

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Kazuhiro NOJIMA ,  Tomohide TEZUKA ,  Atsushi ONISHI ,  Kazuhiro YAMADA ,  Shigeki NOJIMA ,  Akira HAMAGUCHI

IPC: G06F17/50 ,  G01N21/956 ,  G06T7/00 ,  G01N21/88

Abstract: An apparatus for inspecting a defect includes a memory storage and a processing unit coupled to the memory storage. The processing unit is configured to acquire pattern data for one or more patterns implemented on a wafer from a storage device, clip a portion that corresponds to the pattern data from a figure indicated by design data to generate design information and one or more circuit patterns, assign a first set of numbers to the one or more patterns of the pattern data, assign a second set of numbers to the one or more circuit patterns of the design information, generate relation information indicative of one or more correspondences between the first set of numbers and the second set of numbers, verify whether or not the one or more patterns indicated by the pattern data constitute a crucial defect based on the relation information, and send a verification result to a device.

公开(公告)号：US20190080445A1

公开(公告)日：2019-03-14

申请号：US15912611

申请日：2018-03-06

Applicant: Toshiba Memory Corporation

Inventor： Atsushi ONISHI ,  Kazuhiro NOJIMA

IPC: G06T7/00

Abstract: According to one embodiment, an SEM inspection apparatus includes an arithmetic processor. The arithmetic processor acquires design data corresponding to an inspection region. The arithmetic processor obtains a resistance component between each of wiring lines included in the inspection region and a portion on a substrate connected thereto, on a basis of the design data. The arithmetic processor obtains a capacitance component between each of the wiring lines included in the inspection region and the portion on the substrate connected thereto, on a basis of the design data. The arithmetic processor color-codes the wiring lines included in the inspection region of the design data, on a basis of a combination of the resistance component and the capacitance component. The arithmetic processor corrects a coordinate deviation between an SEM image and the color-coded design data by performing pattern matching between the color-coded design data and the SEM image.

公开(公告)号：US20190081053A1

公开(公告)日：2019-03-14

申请号：US15909568

申请日：2018-03-01

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Kazuhiro NOJIMA ,  Megumi SHIBATA ,  Tomonori KAJINO ,  Taro SHIOKAWA

IPC: H01L27/11556 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11582 ,  H01L21/66 ,  H01L23/535 ,  G11C16/04

Abstract: According to one embodiment, there is provided a memory device which includes a plurality of elements that include three-dimensionally arranged memory cells, a transistor that is electrically connected to at least one of the plurality of elements, an inspection pad that is connected in series to at least one of the plurality of elements through the transistor, and a wiring that is electrically connected to the inspection pad and a gate of the transistor and capable of supplying a common potential to both the inspection pad and the transistor for turning the transistor to an OFF state.

公开(公告)号：US20180269203A1

公开(公告)日：2018-09-20

申请号：US15694740

申请日：2017-09-01

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Kazuhiro NOJIMA

IPC: H01L27/06 ,  H01L49/02 ,  H01L27/115

CPC classification number: H01L27/0688 ,  H01L23/5223 ,  H01L27/115 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11575 ,  H01L27/11582 ,  H01L28/60

Abstract: A capacitor includes a plurality of first electrode layers stacked in a first direction, a first conductor extending in the first direction through the plurality of first electrode layers, and a first insulating layer extending in the first direction along the first conductor and located between the first conductor and the plurality of first electrode layers. The capacitor includes a first capacitance provided between the first conductor and the plurality of first electrode layers.

公开(公告)号：US20200098782A1

公开(公告)日：2020-03-26

申请号：US16283589

申请日：2019-02-22

Applicant: Toshiba Memory Corporation

Inventor： Kazuhiro NOJIMA ,  Kojiro SHIMIZU

IPC: H01L27/11582 ,  G11C5/06 ,  H01L27/1157 ,  H01L27/11573

Abstract: A a semiconductor storage device includes a logic circuit formed on a substrate, a first area formed on the logic circuit and has a plurality of first insulating layers and a plurality of conductive layers alternatively stacked in a first direction, a plurality of memory pillars MP which extend in the first area in the first direction, a second area which is formed on the logic circuit and has the plurality of first insulating layers 33 and a plurality of second insulating layers alternately stacked in the first direction, and a contact ping CP1 which extends in the second area in the first direction and is connected to the logic circuit.