公开(公告)号：US20190081053A1

公开(公告)日：2019-03-14

申请号：US15909568

申请日：2018-03-01

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Kazuhiro NOJIMA ,  Megumi SHIBATA ,  Tomonori KAJINO ,  Taro SHIOKAWA

IPC: H01L27/11556 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11582 ,  H01L21/66 ,  H01L23/535 ,  G11C16/04

Abstract: According to one embodiment, there is provided a memory device which includes a plurality of elements that include three-dimensionally arranged memory cells, a transistor that is electrically connected to at least one of the plurality of elements, an inspection pad that is connected in series to at least one of the plurality of elements through the transistor, and a wiring that is electrically connected to the inspection pad and a gate of the transistor and capable of supplying a common potential to both the inspection pad and the transistor for turning the transistor to an OFF state.