公开(公告)号：US20190081053A1

公开(公告)日：2019-03-14

申请号：US15909568

申请日：2018-03-01

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Kazuhiro NOJIMA ,  Megumi SHIBATA ,  Tomonori KAJINO ,  Taro SHIOKAWA

IPC: H01L27/11556 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11582 ,  H01L21/66 ,  H01L23/535 ,  G11C16/04

Abstract: According to one embodiment, there is provided a memory device which includes a plurality of elements that include three-dimensionally arranged memory cells, a transistor that is electrically connected to at least one of the plurality of elements, an inspection pad that is connected in series to at least one of the plurality of elements through the transistor, and a wiring that is electrically connected to the inspection pad and a gate of the transistor and capable of supplying a common potential to both the inspection pad and the transistor for turning the transistor to an OFF state.

公开(公告)号：US20200303402A1

公开(公告)日：2020-09-24

申请号：US16530221

申请日：2019-08-02

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Shigeki KOBAYASHI ,  Taro SHIOKAWA ,  Masahisa SONODA

IPC: H01L27/11582 ,  G11C5/06 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11519 ,  H01L27/11565

Abstract: A semiconductor memory device includes a plurality of first conductor layers that are stacked in a first direction; a first pillar including a first semiconductor layer and extending through the first conductor layers in the first direction; a first charge storage layer that is provided between the first conductor layers and the first semiconductor layer; a plurality of second conductor layers that are stacked in the first direction above an uppermost conductor layer of the first conductor layers; a second pillar including a second semiconductor layer and extending through the second conductor layers in the first direction, the second semiconductor layer electrically connected to the first semiconductor layer; and a conductor pillar or film extending in the first direction through the second conductor layers other than a lowermost layer of the second conductor layers and being in contact with a respective upper surface of each of the second conductor layers.

公开(公告)号：US20200292387A1

公开(公告)日：2020-09-17

申请号：US16561473

申请日：2019-09-05

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Taro SHIOKAWA

IPC: G01J3/28 ,  G01J3/02 ,  G06F11/30 ,  G01N21/21 ,  G01N21/31

Abstract: According to one embodiment, there is provided a measuring apparatus including a measurement section and a control section. The measurement section is configured to acquire a response from a sample. The control section is configured to compare a loading obtained by performing principal component analysis in advance with a first evaluation-use loading obtained by performing principal component analysis onto the response acquired from the sample, and to generate a first reliability index for measurement using principal component analysis, in accordance with a comparison result.