公开(公告)号：US10658480B2

公开(公告)日：2020-05-19

申请号：US16124114

申请日：2018-09-06

申请人： TOSHIBA MEMORY CORPORATION

发明人： Ryuji Ohba

IPC分类号： H01L29/423 ,  H01L29/66 ,  H01L29/51 ,  H01L27/11582 ,  H01L27/11556 ,  H01L27/11514 ,  H01L27/11578 ,  H01L27/11551

摘要： A memory device includes plural electrode layers stacked in a first direction, a semiconductor layer interacting with the plural electrode layers and extending in the first direction, a first insulating film provided between the semiconductor layer and at least one electrode layer and extending along the semiconductor layer in the first direction, and a charge trapping film provided between the electrode layer and the first insulating film. The memory device further includes a second insulating film provided between the charge trapping film and the first insulating film and in contact with the first insulating film. In a flat band state, the charge trapping film has a first trap level located at a level deeper than a conduction band of the semiconductor layer and the second insulating film has a second trap level that is closer to the conduction band of the semiconductor layer than the first trap level.

公开(公告)号：US10903228B2

公开(公告)日：2021-01-26

申请号：US16114074

申请日：2018-08-27

申请人： TOSHIBA MEMORY CORPORATION

发明人： Hiroki Sasaki ,  Atsushi Murakoshi ,  Ryuji Ohba

IPC分类号： H01L27/11582 ,  H01L27/1157 ,  H01L23/532 ,  G11C7/06 ,  H01L21/768 ,  G11C8/14 ,  H01L29/792 ,  G11C8/10 ,  G11C7/18 ,  H01L29/788 ,  H01L27/11556

摘要： A semiconductor storage device includes a semiconductor substrate and a plurality of first wiring layers stacked above the semiconductor substrate in a first direction orthogonal to the semiconductor substrate, and extending in a second direction intersecting the first direction and parallel to the semiconductor substrate. The device further includes a first memory pillar including a semiconductor layer and a first insulation layer extending in the first direction, the first insulation layer provided between the plurality of first wiring layers and the semiconductor layer so as to contact the semiconductor layer, and charge storage layers provided respectively between the plurality of first wiring layers and the first insulation layer. One or more of the charge storage layers is in contact with the first insulation layer. A plurality of second insulation layers is provided between each of the plurality of first wiring layers and each of the charge storage layers.