公开(公告)号：US10268399B2

公开(公告)日：2019-04-23

申请号：US15445147

申请日：2017-02-28

申请人： TOSHIBA MEMORY CORPORATION

发明人： Akihiro Nagatani ,  Takahiro Miomo ,  Hajime Yamazaki ,  Shinji Yonezawa ,  Mitsunori Tadokoro

IPC分类号： G06F3/06 ,  G06F9/54 ,  G06F12/10 ,  G06F12/109

摘要： According to one embodiment, a memory system includes a first memory including a message queue having first to nth addresses (n≥2, n is natural number), a first pointer showing one of the first to nth addresses, and a second pointer showing one of the first to nth addresses, a monitor unit which detects whether the first and second pointers show the first address, and a processing unit which changes an address shown by the first pointer from the first address to an ith address (n≥i≥2, i is natural number) when the first and second pointers show the first address. An address shown by the second pointer is incremented from the first address to a (j+1)th address (j≥1, j is natural number) when first to jth messages are queued in the first to jth addresses.

公开(公告)号：US10949090B2

公开(公告)日：2021-03-16

申请号：US15693411

申请日：2017-08-31

申请人： Toshiba Memory Corporation

发明人： Shinji Yonezawa

IPC分类号： G06F3/06 ,  G06F12/02 ,  G06F12/0831 ,  G06F12/128 ,  G06F12/0808 ,  G06F12/0895 ,  G06F12/0897 ,  G06F12/0891 ,  G06F12/0864 ,  G11C7/10 ,  G11C8/06 ,  G11C8/18 ,  G11C8/08

摘要： A memory system which is accessible to a host device includes a volatile memory, a nonvolatile memory, and a memory controller that controls the volatile memory and the nonvolatile memory. The memory controller stores first data, which is stored in the volatile memory, in the nonvolatile memory, each time the memory controller stores second data, which is stored in the volatile memory, in the nonvolatile memory. The first data indicates a logical address and a deletion range designated by a deletion request received from the host device, and the second data is designated by a write request received from the host device.