公开(公告)号：US20180076264A1

公开(公告)日：2018-03-15

申请号：US15465034

申请日：2017-03-21

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Takahiko SASAKI ,  Takeshi YAMAGUCHI

IPC: H01L27/24 ,  H01L45/00

CPC classification number: H01L27/2436 ,  G11C8/12 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/0033 ,  G11C2213/71 ,  G11C2213/77 ,  H01L45/1233

Abstract: A semiconductor memory device according to an embodiment includes: a first wiring line extending in a first direction; a second wiring line extending in a second direction, the second direction intersecting the first direction; a variable resistance film disposed at an intersection of the first wiring line and the second wiring line; a channel body disposed at a first end of the first wiring line; a third wiring line electrically connected to the first wiring line via the channel body; and a gate wiring line extending in the first direction and facing the channel body from the second direction.