公开(公告)号：US20180013061A1

公开(公告)日：2018-01-11

申请号：US15644282

申请日：2017-07-07

Applicant: Toshiba Memory Corporation

Inventor： Hiroyuki FUKUMIZU ,  Takeshi YAMAGUCHI

IPC: H01L45/00 ,  G11C13/00 ,  H01L27/24

CPC classification number: H01L45/10 ,  G11C13/0007 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/004 ,  G11C2013/0042 ,  H01L27/2409 ,  H01L27/2463 ,  H01L27/2481 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/1273 ,  H01L45/146

Abstract: According to one embodiment, a memory device includes a stacked body. The stacked body includes first and second electrodes, and an oxide layer provided between the first and second electrodes. The second electrode includes a semiconductor layer, and a metal-containing region including at least one of first or second metallic element and being provided between at least a portion of the semiconductor layer and at least a portion of the oxide layer. The first metallic element includes at least one selected from Pt, Pd, Ir, Ru, Re, and Os. The second metallic element includes at least one selected Ti, W, Mo, and Ta. The stacked body has first and second states. The first state is obtained by causing a current to flow in the stacked body from the second toward first electrode. The second state is obtained by causing a current to flow from the first toward second electrode.

公开(公告)号：US20180006089A1

公开(公告)日：2018-01-04

申请号：US15706598

申请日：2017-09-15

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Natsuki FUKUDA ,  Mutsumi OKAJIMA ,  Atsushi OGA ,  Toshiharu TANAKA ,  Takeshi YAMAGUCHI ,  Takeshi TAKAGI ,  Masanori KOMURA

IPC: H01L27/24 ,  H01L27/11582 ,  H01L27/11578 ,  H01L27/11575 ,  H01L27/11573 ,  H01L27/11556 ,  H01L21/311 ,  H01L27/11551 ,  H01L21/822 ,  H01L21/768 ,  H01L21/3213 ,  H01L29/792 ,  H01L27/1157

CPC classification number: H01L27/2481 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/76805 ,  H01L21/76816 ,  H01L21/76831 ,  H01L21/8221 ,  H01L23/5226 ,  H01L23/5329 ,  H01L27/0688 ,  H01L27/101 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11578 ,  H01L27/11582 ,  H01L27/2454 ,  H01L27/249 ,  H01L29/7926

Abstract: A semiconductor device according to an embodiment includes: a stacked body including a plurality of first conductive films stacked via an inter-layer insulating film;a first conductive body contacting the stacked body to extend in a stacking direction; and a plurality of first insulating films in the same layers as the first conductive films and disposed between the first conductive body and the first conductive films, the first conductive body including a projecting part that projects along tops of one of the first insulating films and one of the first conductive films, and a side surface of the projecting part contacting an upper surface of the one of the first conductive films.

公开(公告)号：US20180233213A1

公开(公告)日：2018-08-16

申请号：US15691714

申请日：2017-08-30

Applicant: Toshiba Memory Corporation

Inventor： Tsutomu MIYAMAE ,  Nariyuki FUKUDA ,  Kazuhito HOSAKA ,  Takeshi YAMAGUCHI ,  Suguru TAHARA ,  Isao OOIGAWA ,  Keitarou MISHIMA ,  Yuichiro SANUKI

IPC: G11C29/38 ,  G11C29/44

CPC classification number: G11C29/38 ,  G11C29/44

Abstract: According to one embodiment, a semiconductor circuit includes a plurality of memories. The memories are connected to one another in series such that an output node of the memory of the first stage is connected to an input node of the memory of the second stage. The semiconductor circuit includes a test circuit that outputs test data to an input node of the memory of the first stage among the plurality of memories, and a comparison circuit that compares data output from an output node of the memory of the final stage among the plurality of memories with expectation value data.

公开(公告)号：US20180076264A1

公开(公告)日：2018-03-15

申请号：US15465034

申请日：2017-03-21

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Takahiko SASAKI ,  Takeshi YAMAGUCHI

IPC: H01L27/24 ,  H01L45/00

CPC classification number: H01L27/2436 ,  G11C8/12 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/0033 ,  G11C2213/71 ,  G11C2213/77 ,  H01L45/1233

Abstract: A semiconductor memory device according to an embodiment includes: a first wiring line extending in a first direction; a second wiring line extending in a second direction, the second direction intersecting the first direction; a variable resistance film disposed at an intersection of the first wiring line and the second wiring line; a channel body disposed at a first end of the first wiring line; a third wiring line electrically connected to the first wiring line via the channel body; and a gate wiring line extending in the first direction and facing the channel body from the second direction.

公开(公告)号：US20170373119A1

公开(公告)日：2017-12-28

申请号：US15465049

申请日：2017-03-21

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Atsushi OGA ,  Mutsumi OKAJIMA ,  Natsuki FUKUDA ,  Takeshi YAMAGUCHI ,  Toshiharu TANAKA ,  Hiroyuki ODE

IPC: H01L27/24 ,  H01L45/00

CPC classification number: H01L27/249 ,  H01L27/2454 ,  H01L45/1226 ,  H01L45/146 ,  H01L45/16

Abstract: A semiconductor memory device according to an embodiment comprises: a semiconductor substrate extending in a first direction and a second direction, the first and second directions intersecting each other; a first wiring line disposed above the semiconductor substrate and extending in the first direction; a second wiring line disposed above the semiconductor substrate and extending in a third direction, the third direction intersecting the first direction and the second direction; a variable resistance film disposed at an intersection of the first wiring line and the second wiring line; a first insulating film disposed aligned with the second wiring line in the first direction; a first film disposed between the first wiring line and the first insulating film; and a second film disposed between the first insulating film and the first film and configured from a material different from that of the first film.