公开(公告)号：US20190088869A1

公开(公告)日：2019-03-21

申请号：US15909125

申请日：2018-03-01

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Yefei HAN ,  Tetsu MOROOKA

IPC: H01L45/00 ,  H01L27/24 ,  G11C7/06 ,  G11C7/12

CPC classification number: H01L45/06 ,  G11C7/06 ,  G11C7/12 ,  G11C13/0007 ,  G11C13/003 ,  G11C13/0033 ,  G11C29/04 ,  G11C29/70 ,  G11C2213/71 ,  G11C2213/76 ,  G11C2213/78 ,  G11C2213/79 ,  H01L27/2436 ,  H01L27/2481 ,  H01L27/249 ,  H01L45/08 ,  H01L45/1226 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/146 ,  H01L45/1608

Abstract: A memory device includes a first conductive layer and a second conductive layer. A variable resistance layer is disposed between the first conductive layer and the second conductive layer and includes a first layer containing a semiconductor or a first metal oxide, and a second layer containing a second metal oxide. A phase-change layer is disposed either between the first conductive layer and the variable resistance layer or between the second conductive layer and the variable resistance layer.