公开(公告)号：US20220002905A1

公开(公告)日：2022-01-06

申请号：US17277378

申请日：2019-09-19

Applicant: TOYO TANSO CO., LTD.

Inventor： Norihito YABUKI ,  Takuya SAKAGUCHI ,  Akiko JINNO ,  Satoru NOGAMI ,  Makoto KITABATAKE

IPC: C30B25/18 ,  H01L21/02 ,  H01L21/324

Abstract: In a method for manufacturing a device fabrication wafer, an SiC epitaxial wafer that is an SiC wafer 40 having a monocrystalline SiC epitaxial layer formed thereon is subjected to a basal plane dislocation density reduction step of reducing the density of basal plane dislocations existing in the epitaxial layer of the SiC epitaxial wafer, to thereby manufacture the device fabrication wafer for use to fabricate a semiconductor device. In the basal plane dislocation density reduction step, the SiC epitaxial wafer is heated under Si vapor pressure for a predetermined time necessary to reduce the density of basal plane dislocations, without formation of a cap layer on the SiC epitaxial wafer, so that the density of basal plane dislocations is reduced with suppression of surface roughening.