公开(公告)号：US20210375613A1

公开(公告)日：2021-12-02

申请号：US17262387

申请日：2019-07-25

Applicant: Toyo Tanso Co., Ltd.

Inventor： Norihito YABUKI ,  Yuji NAKASHIMA ,  Takuya SAKAGUCHI ,  Satoru NOGAMI ,  Makoto KITABATAKE

IPC: H01L21/02 ,  C30B33/12 ,  C30B29/36 ,  B24B37/04

Abstract: In a method for manufacturing an SiC wafer, a work-affected layer removal step of removing a work-affected layer generated in a surface and inside of an SiC wafer is performed, so that the SiC wafer from which the work-affected layer is at least partially removed is manufactured. In the work-affected layer removal step, the SiC wafer having undergone a polishing step is etched with an etching amount of 10 μm or less by being heated under Si vapor pressure so that the work-affected layer is removed. In the polishing step, an oxidizer is used to produce a reaction product in the SiC wafer while abrasive grains are used to remove the reaction product. In the SiC wafer having undergone the polishing step, an internal stress caused by the work-affected layer is present at a location inner than the work-affected layer, and an internal stress of the SiC wafer is reduced by removing the work-affected layer in the work-affected layer removal step.

公开(公告)号：US20220002905A1

公开(公告)日：2022-01-06

申请号：US17277378

申请日：2019-09-19

Applicant: TOYO TANSO CO., LTD.

Inventor： Norihito YABUKI ,  Takuya SAKAGUCHI ,  Akiko JINNO ,  Satoru NOGAMI ,  Makoto KITABATAKE

IPC: C30B25/18 ,  H01L21/02 ,  H01L21/324

Abstract: In a method for manufacturing a device fabrication wafer, an SiC epitaxial wafer that is an SiC wafer 40 having a monocrystalline SiC epitaxial layer formed thereon is subjected to a basal plane dislocation density reduction step of reducing the density of basal plane dislocations existing in the epitaxial layer of the SiC epitaxial wafer, to thereby manufacture the device fabrication wafer for use to fabricate a semiconductor device. In the basal plane dislocation density reduction step, the SiC epitaxial wafer is heated under Si vapor pressure for a predetermined time necessary to reduce the density of basal plane dislocations, without formation of a cap layer on the SiC epitaxial wafer, so that the density of basal plane dislocations is reduced with suppression of surface roughening.

公开(公告)号：US20210040643A1

公开(公告)日：2021-02-11

申请号：US16611903

申请日：2018-05-11

Applicant: TOYO TANSO CO., LTD.

Inventor： Takuya SAKAGUCHI ,  Masato SHINOHARA ,  Satoru NOGAMI

IPC: C30B25/12 ,  C23C16/458 ,  C30B23/06 ,  C30B25/20 ,  C30B29/36 ,  C23C16/32 ,  H01L21/02

Abstract: A susceptor is a component for placing a SiC substrate in forming an epitaxial layer on a main surface of the SiC substrate. In this susceptor, a support surface and a recess are formed. The support surface is formed on lower position than an upper surface of the susceptor and supports an outer circumferential of the rear face of the SiC substrate. The recess is formed in the inside of the diametrical direction than the support surface, and at least the surface is made of a tantalum carbide, the depth of that is not in contact with the rear face of the Sic substrate in forming the epitaxial layer.

公开(公告)号：US20210301421A1

公开(公告)日：2021-09-30

申请号：US17263149

申请日：2019-07-24

Applicant: DENSO CORPORATION ,  TOYO TANSO CO., LTD. ,  TOYOTA TSUSHO CORPORATION

Inventor： Masatake NAGAYA ,  Takahiro KANDA ,  Takeshi OKAMOTO ,  Satoshi TORIMI ,  Satoru NOGAMI ,  Makoto KITABATAKE

IPC: C30B29/36 ,  H01L21/02 ,  C30B33/12 ,  C30B11/02 ,  C30B33/10 ,  B28D5/04

Abstract: An object is to provide a SiC wafer in which a detection rate of an optical sensor can improved and a SiC wafer manufacturing method.
The method includes: a satin finishing process S141 of satin-finishing at least a back surface 22 of a SiC wafer 20; an etching process 21 of etching at least the back surface 22 of the SiC wafer 20 by heating under Si vapor pressure after the satin finishing process S141; and a mirror surface processing process S31 of mirror-processing a main surface 21 of the SiC wafer 20 after the etching process S21. Accordingly, it is possible to obtain a SiC wafer having the mirror-finished main surface 21 and the satin-finished back surface 22.