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    Network unit with power saving mode inhibit based on interconnection relationship to neighboring nodes which is stored on the unit
    1.
    发明授权
    Network unit with power saving mode inhibit based on interconnection relationship to neighboring nodes which is stored on the unit 有权
    具有省电模式的网络单元基于与存储在单元上的相邻节点的互连关系而禁止

    公开(公告)号：US06604201B1

    公开(公告)日：2003-08-05

    申请号：US09428277

    申请日：1999-10-27

    申请人： Satoshi Takahashi ,  Hiroyuki Yamauchi ,  Hironori Akamatsu ,  Tadahiro Yoshida ,  Yutaka Terada ,  Yukio Arima ,  Takashi Hirata ,  Yoshihide Komatsu

    发明人： Satoshi Takahashi ,  Hiroyuki Yamauchi ,  Hironori Akamatsu ,  Tadahiro Yoshida ,  Yutaka Terada ,  Yukio Arima ,  Takashi Hirata ,  Yoshihide Komatsu

    IPC分类号： G06F132

    CPC分类号： H04L12/12 ,  Y02D50/20 ,  Y02D50/40

    摘要： A power-saving network unit, which is connected to a network made up of a plurality of power-saving network units, includes: network monitoring means; network information memory; power-saving mode setting means; peripheral I/O interface; and digital processor. The network monitoring means monitors a topology of the network, or the interconnection relationship among the power-saving network units. Every time the network has been modified, the network monitoring means stores the modified network topology on the network information memory. The power-saving mode setting means receives the network information stored on the network information memory. If the power-saving network unit is a master or relay node in the network, then the power-saving mode setting means locks the peripheral I/O interface and digital processor of the power-saving network unit to the normal operation mode and prohibits these sections from entering the power-saving mode.

    摘要翻译： 连接到由多个省电网络单元组成的网络的节电网单元包括：网络监控装置; 网络信息记忆; 省电模式设定手段; 外设I / O接口; 和数字处理器。 网络监控装置监控网络的拓扑结构，或节能网络单元之间的互连关系。 每当网络被修改时，网络监控装置将修改的网络拓扑存储在网络信息存储器上。 省电模式设置装置接收存储在网络信息存储器上的网络信息。 如果省电网络单元是网络中的主节点或中继节点，则省电模式设置装置将节电网络单元的外围I / O接口和数字处理器锁定到正常操作模式，并禁止这些 部分进入省电模式。

    Voltage control circuit network device and method of detecting voltage
    3.
    发明授权
    Voltage control circuit network device and method of detecting voltage 有权
    电压控制电路网络装置及电压检测方法

    公开(公告)号：US06498519B1

    公开(公告)日：2002-12-24

    申请号：US09498339

    申请日：2000-02-04

    申请人： Yutaka Terada ,  Hiroyuki Yamauchi ,  Hironori Akamatsu ,  Tadahiro Yoshida ,  Satoshi Takahashi ,  Takashi Hirata ,  Yukio Arima ,  Yoshihide Komatsu

    发明人： Yutaka Terada ,  Hiroyuki Yamauchi ,  Hironori Akamatsu ,  Tadahiro Yoshida ,  Satoshi Takahashi ,  Takashi Hirata ,  Yukio Arima ,  Yoshihide Komatsu

    IPC分类号： H03K5153

    CPC分类号： G01R19/16547

    摘要： A voltage control circuit for implementing, e.g., the CPS function in which a high-accuracy comparison is performed between a high external voltage and a reference voltage. A diode-connected transistor converts the external voltage to a voltage lower than the external voltage in conjunction with an external voltage dropping resistor. A comparator compares the converted voltage with a specified comparison voltage. The size of the transistor is determined such that the ratio of an increment of the converted voltage to an increment of the external voltage is sufficiently high in a comparison region in which the external voltage is close to the reference voltage. A clamping circuit clamps the converted voltage with a specified limit voltage such that the converted voltage does not exceed the withstand voltage of the circuit.

    摘要翻译： 一种用于实现例如在高外部电压和参考电压之间进行高精度比较的CPS功能的电压控制电路。 二极管连接的晶体管将外部电压转换为低于外部电压的电压，并结合外部降压电阻。 比较器将转换的电压与指定的比较电压进行比较。 确定晶体管的尺寸，使得在外部电压接近参考电压的比较区域中，转换电压的增量与外部电压的增量的比率足够高。 钳位电路以转换后的电压将指定的极限电压钳位，使转换后的电压不超过电路的耐压。

    Semiconductor integrated circuit and semiconductor integrated circuit system having serially interconnectable data buses
    4.
    发明授权
    Semiconductor integrated circuit and semiconductor integrated circuit system having serially interconnectable data buses 有权
    具有串行可互连数据总线的半导体集成电路和半导体集成电路系统

    公开(公告)号：US06297675B1

    公开(公告)日：2001-10-02

    申请号：US09478530

    申请日：2000-01-06

    申请人： Hironori Akamatsu ,  Yutaka Terada ,  Takashi Hirata ,  Yukio Arima ,  Satoshi Takahashi ,  Tadahiro Yoshida ,  Yoshihide Komatsu ,  Hiroyuki Yamauchi

    发明人： Hironori Akamatsu ,  Yutaka Terada ,  Takashi Hirata ,  Yukio Arima ,  Satoshi Takahashi ,  Tadahiro Yoshida ,  Yoshihide Komatsu ,  Hiroyuki Yamauchi

    IPC分类号： H03B100

    CPC分类号： H03K19/018514 ,  Y10T307/549

    摘要： A data line pair and a strobe line pair are provided between first and second chips to exchange data therebetween. The first chip includes an output circuit and a controller for controlling the output circuit. The second chip includes an input circuit. For example, the output circuit supplies a direct current from a power supply to one of the data lines. Then, the input circuit feeds back the received current to the output circuit through a pair of terminal resistors and the other data line. Subsequently, the output circuit supplies the fed back direct current to one of the strobe lines. In response, the input circuit feeds back the received current again to the output circuit through another pair of terminal resistors and the other strobe line. And then the fed back current is drained to the ground. Thus, compared to driving the data and strobe line pairs separately with the same amount of current supplied, the current dissipation can be halved. In this manner, the present invention is applicable to reduction of current dissipation when data should be transmitted at high speeds through multiple data bus pairs that are driven with a current supplied.

    摘要翻译： 在第一和第二芯片之间提供数据线对和选通线对，以在它们之间交换数据。 第一芯片包括输出电路和用于控制输出电路的控制器。 第二芯片包括输入电路。 例如，输出电路将电流从电源提供给数据线之一。 然后，输入电路通过一对端子电阻和另一条数据线将接收的电流反馈到输出电路。 随后，输出电路将反馈的直流电流提供给选通线之一。 作为响应，输入电路通过另一对端子电阻器和另一个选通线路将接收到的电流再次反馈到输出电路。 然后将反馈电流排到地面。 因此，与以相同的电流量驱动数据和选通线对相比，电流消耗可以减半。 以这种方式，本发明可应用于当通过以所提供的电流驱动的多个数据总线对以高速传输数据时，减少电流消耗。

    Common mode bias generator
    5.
    发明授权
    Common mode bias generator 有权
    共模偏置发生器

    公开(公告)号：US06262568B1

    公开(公告)日：2001-07-17

    申请号：US09734191

    申请日：2000-12-12

    申请人： Yoshihide Komatsu ,  Hironori Akamatsu ,  Takashi Hirata ,  Satoshi Takahashi ,  Yutaka Terada

    发明人： Yoshihide Komatsu ,  Hironori Akamatsu ,  Takashi Hirata ,  Satoshi Takahashi ,  Yutaka Terada

    IPC分类号： G05F304

    CPC分类号： G05F3/205

    摘要： An inventive potential generator generates a predetermined potential and includes first operational amplifier, current supply circuit and current sink circuit. A first reference potential is applied to the non-inverting input terminal of the first amplifier and a potential at the output node of the first amplifier is not only applied to the inverting input terminal of the first amplifier but also used as the output of the generator. The current supply circuit supplies a current to the output node of the first amplifier if the potential at the output node of the first amplifier is lower than a predefined level. And the current sink circuit drains a current from the output node of the first amplifier if the potential at the output node of the first amplifier is higher than the predefined level.

    摘要翻译： 本发明的潜在发生器产生预定电位并且包括第一运算放大器，电流供应电路和电流吸收电路。 第一参考电位被施加到第一放大器的非反相输入端，并且第一放大器的输出节点处的电位不仅被施加到第一放大器的反相输入端，而且还用作发生器的输出 。 如果第一放大器的输出节点处的电位低于预定义电平，则电流供应电路向第一放大器的输出节点提供电流。 并且如果第一放大器的输出节点处的电位高于预定义电平，则电流吸收电路从第一放大器的输出节点漏出电流。

    Semiconductor integrated circuit realizing electrical interface
    6.
    发明授权
    Semiconductor integrated circuit realizing electrical interface 有权
    半导体集成电路实现电接口

    公开(公告)号：US06404370B2

    公开(公告)日：2002-06-11

    申请号：US09828936

    申请日：2001-04-10

    申请人： Yutaka Terada ,  Hironori Akamatsu ,  Satoshi Takahashi ,  Takashi Hirata ,  Yoshihide Komatsu

    发明人： Yutaka Terada ,  Hironori Akamatsu ,  Satoshi Takahashi ,  Takashi Hirata ,  Yoshihide Komatsu

    IPC分类号： H03M300

    CPC分类号： H04L12/40052 ,  H04L12/40032

    摘要： A semiconductor integrated circuit includes receiver, potential sensor and output fixing circuit. The receiver receives a differential signal that has been transmitted through a twisted pair of signal lines, and outputs a signal in accordance with the differential signal. The potential sensor senses a variation in in-phase potential of the differential signal transmitted through the twisted pair. And the output fixing circuit fixes an output of the receiver at a certain value if the variation sensed by the potential sensor is equal to or greater than a predetermined level. In this configuration, once the variation in the in-phase potential of the differential signal has reached the predetermined level, the output of the receiver is fixed at the certain value. Accordingly, even if the receiver operates erroneously due to the in-phase potential variation, the erroneous output of the receiver is not supplied to the next stage like a digital section.

    摘要翻译： 半导体集成电路包括接收器，电位传感器和输出固定电路。 接收机接收通过双绞信号线发送的差分信号，并根据差分信号输出信号。 电位传感器检测通过双绞线传输的差分信号的同相电位变化。 如果由电位传感器感测到的变化量等于或大于预定水平，则输出定影电路将接收器的输出固定在一定值。 在该配置中，一旦差分信号的同相电位的变化已经达到预定电平，则接收器的输出被固定在该特定值。 因此，即使接收器由于同相电位变化而错误地操作，接收机的错误输出也不像数字部分那样被提供给下一个级。

    Output driver with current compensation circuit for variation of common mode voltage
    7.
    发明授权
    Output driver with current compensation circuit for variation of common mode voltage 失效
    具有电流补偿电路的输出驱动器，用于变化共模电压

    公开(公告)号：US06329843B1

    公开(公告)日：2001-12-11

    申请号：US09684979

    申请日：2000-10-10

    申请人： Takashi Hirata ,  Hironori Akamatsu ,  Satoshi Takahashi ,  Yutaka Terada ,  Yoshihide Komatsu

    发明人： Takashi Hirata ,  Hironori Akamatsu ,  Satoshi Takahashi ,  Yutaka Terada ,  Yoshihide Komatsu

    IPC分类号： H03K190175

    CPC分类号： H04L25/028 ,  H04L25/0276

    摘要： A current driver, a common mode voltage monitoring circuit and a current compensator are provided to drive a twisted pair cable, which is made up of two signal lines coupled to a terminal bias voltage through respective terminal resistors. The common mode voltage monitoring circuit monitors a difference between a common mode voltage of the twisted pair cable and a supply voltage level for the current driver. And the current compensator is coupled to the twisted pair cable to compensate for an output current of the current driver in accordance with a result of monitoring performed by the common mode voltage monitoring circuit. If the current driver has decreased its current drivability due to a drop of the supply voltage level of the current driver or a variation in the common mode voltage of the twisted pair cable, then the current compensator compensates for the decrease. Thus, the current driver can continuously operate in a broad voltage range to supply a constant current.

    摘要翻译： 提供电流驱动器，共模电压监视电路和电流补偿器来驱动双绞线电缆，双绞线电缆由通过相应的终端电阻器耦合到端子偏置电压的两根信号线组成。 共模电压监视电路监视双绞线电缆的共模电压与当前驱动器的电源电压差之间的差异。 并且电流补偿器耦合到双绞线电缆，以根据共模电压监视电路执行的监视结果补偿电流驱动器的输出电流。 如果当前的驱动器由于当前驱动器的电源电压下降或双绞线的共模电压的变化而降低其电流驱动能力，则电流补偿器补偿减小。 因此，电流驱动器可以在宽电压范围内连续工作以提供恒定电流。

    Semiconductor memory
    9.
    发明授权
    Semiconductor memory 失效
    半导体存储器

    公开(公告)号：US6009024A

    公开(公告)日：1999-12-28

    申请号：US46880

    申请日：1998-03-24

    申请人： Takashi Hirata ,  Hiroyuki Yamauchi ,  Hironori Akamatsu ,  Keiichi Kusumoto ,  Toru Iwata ,  Satoshi Takahashi ,  Yutaka Terada

    发明人： Takashi Hirata ,  Hiroyuki Yamauchi ,  Hironori Akamatsu ,  Keiichi Kusumoto ,  Toru Iwata ,  Satoshi Takahashi ,  Yutaka Terada

    IPC分类号： G11C7/06 ,  G11C7/00

    CPC分类号： G11C7/06

    摘要： A semiconductor memory of the present invention includes: a plurality of memory cells; a pair of local bit lines connected to the plurality of memory cells; a local sense amplifier for amplifying a potential difference between the pair of local bit lines; a pair of global bit lines electrically connected to the pair of local bit lines through a switch; and a global sense amplifier for amplifying a potential difference between the pair of global bit lines, wherein the local sense amplifier includes a plurality of transistors, each of the plurality of transistors included in the local sense amplifier is a transistor of a first conductivity type, and the global sense amplifier includes a transistor of a second conductivity type different from the first conductivity type.

    摘要翻译： 本发明的半导体存储器包括：多个存储单元; 连接到所述多个存储器单元的一对局部位线; 本地读出放大器，用于放大一对局部位线之间的电位差; 一对全局位线通过开关电连接到该对局部位线; 以及用于放大所述一对全局位线之间的电位差的全局读出放大器，其中所述局部读出放大器包括多个晶体管，所述局部读出放大器中包括的所述多个晶体管中的每一个是第一导电类型的晶体管， 并且全球感测放大器包括不同于第一导电类型的第二导电类型的晶体管。