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    Network unit with power saving mode inhibit based on interconnection relationship to neighboring nodes which is stored on the unit
    1.
    发明授权
    Network unit with power saving mode inhibit based on interconnection relationship to neighboring nodes which is stored on the unit 有权
    具有省电模式的网络单元基于与存储在单元上的相邻节点的互连关系而禁止

    公开(公告)号：US06604201B1

    公开(公告)日：2003-08-05

    申请号：US09428277

    申请日：1999-10-27

    申请人： Satoshi Takahashi ,  Hiroyuki Yamauchi ,  Hironori Akamatsu ,  Tadahiro Yoshida ,  Yutaka Terada ,  Yukio Arima ,  Takashi Hirata ,  Yoshihide Komatsu

    发明人： Satoshi Takahashi ,  Hiroyuki Yamauchi ,  Hironori Akamatsu ,  Tadahiro Yoshida ,  Yutaka Terada ,  Yukio Arima ,  Takashi Hirata ,  Yoshihide Komatsu

    IPC分类号： G06F132

    CPC分类号： H04L12/12 ,  Y02D50/20 ,  Y02D50/40

    摘要： A power-saving network unit, which is connected to a network made up of a plurality of power-saving network units, includes: network monitoring means; network information memory; power-saving mode setting means; peripheral I/O interface; and digital processor. The network monitoring means monitors a topology of the network, or the interconnection relationship among the power-saving network units. Every time the network has been modified, the network monitoring means stores the modified network topology on the network information memory. The power-saving mode setting means receives the network information stored on the network information memory. If the power-saving network unit is a master or relay node in the network, then the power-saving mode setting means locks the peripheral I/O interface and digital processor of the power-saving network unit to the normal operation mode and prohibits these sections from entering the power-saving mode.

    摘要翻译： 连接到由多个省电网络单元组成的网络的节电网单元包括：网络监控装置; 网络信息记忆; 省电模式设定手段; 外设I / O接口; 和数字处理器。 网络监控装置监控网络的拓扑结构，或节能网络单元之间的互连关系。 每当网络被修改时，网络监控装置将修改的网络拓扑存储在网络信息存储器上。 省电模式设置装置接收存储在网络信息存储器上的网络信息。 如果省电网络单元是网络中的主节点或中继节点，则省电模式设置装置将节电网络单元的外围I / O接口和数字处理器锁定到正常操作模式，并禁止这些 部分进入省电模式。

    Voltage control circuit network device and method of detecting voltage
    3.
    发明授权
    Voltage control circuit network device and method of detecting voltage 有权
    电压控制电路网络装置及电压检测方法

    公开(公告)号：US06498519B1

    公开(公告)日：2002-12-24

    申请号：US09498339

    申请日：2000-02-04

    申请人： Yutaka Terada ,  Hiroyuki Yamauchi ,  Hironori Akamatsu ,  Tadahiro Yoshida ,  Satoshi Takahashi ,  Takashi Hirata ,  Yukio Arima ,  Yoshihide Komatsu

    发明人： Yutaka Terada ,  Hiroyuki Yamauchi ,  Hironori Akamatsu ,  Tadahiro Yoshida ,  Satoshi Takahashi ,  Takashi Hirata ,  Yukio Arima ,  Yoshihide Komatsu

    IPC分类号： H03K5153

    CPC分类号： G01R19/16547

    摘要： A voltage control circuit for implementing, e.g., the CPS function in which a high-accuracy comparison is performed between a high external voltage and a reference voltage. A diode-connected transistor converts the external voltage to a voltage lower than the external voltage in conjunction with an external voltage dropping resistor. A comparator compares the converted voltage with a specified comparison voltage. The size of the transistor is determined such that the ratio of an increment of the converted voltage to an increment of the external voltage is sufficiently high in a comparison region in which the external voltage is close to the reference voltage. A clamping circuit clamps the converted voltage with a specified limit voltage such that the converted voltage does not exceed the withstand voltage of the circuit.

    摘要翻译： 一种用于实现例如在高外部电压和参考电压之间进行高精度比较的CPS功能的电压控制电路。 二极管连接的晶体管将外部电压转换为低于外部电压的电压，并结合外部降压电阻。 比较器将转换的电压与指定的比较电压进行比较。 确定晶体管的尺寸，使得在外部电压接近参考电压的比较区域中，转换电压的增量与外部电压的增量的比率足够高。 钳位电路以转换后的电压将指定的极限电压钳位，使转换后的电压不超过电路的耐压。

    Semiconductor integrated circuit and semiconductor integrated circuit system having serially interconnectable data buses
    4.
    发明授权
    Semiconductor integrated circuit and semiconductor integrated circuit system having serially interconnectable data buses 有权
    具有串行可互连数据总线的半导体集成电路和半导体集成电路系统

    公开(公告)号：US06297675B1

    公开(公告)日：2001-10-02

    申请号：US09478530

    申请日：2000-01-06

    申请人： Hironori Akamatsu ,  Yutaka Terada ,  Takashi Hirata ,  Yukio Arima ,  Satoshi Takahashi ,  Tadahiro Yoshida ,  Yoshihide Komatsu ,  Hiroyuki Yamauchi

    发明人： Hironori Akamatsu ,  Yutaka Terada ,  Takashi Hirata ,  Yukio Arima ,  Satoshi Takahashi ,  Tadahiro Yoshida ,  Yoshihide Komatsu ,  Hiroyuki Yamauchi

    IPC分类号： H03B100

    CPC分类号： H03K19/018514 ,  Y10T307/549

    摘要： A data line pair and a strobe line pair are provided between first and second chips to exchange data therebetween. The first chip includes an output circuit and a controller for controlling the output circuit. The second chip includes an input circuit. For example, the output circuit supplies a direct current from a power supply to one of the data lines. Then, the input circuit feeds back the received current to the output circuit through a pair of terminal resistors and the other data line. Subsequently, the output circuit supplies the fed back direct current to one of the strobe lines. In response, the input circuit feeds back the received current again to the output circuit through another pair of terminal resistors and the other strobe line. And then the fed back current is drained to the ground. Thus, compared to driving the data and strobe line pairs separately with the same amount of current supplied, the current dissipation can be halved. In this manner, the present invention is applicable to reduction of current dissipation when data should be transmitted at high speeds through multiple data bus pairs that are driven with a current supplied.

    摘要翻译： 在第一和第二芯片之间提供数据线对和选通线对，以在它们之间交换数据。 第一芯片包括输出电路和用于控制输出电路的控制器。 第二芯片包括输入电路。 例如，输出电路将电流从电源提供给数据线之一。 然后，输入电路通过一对端子电阻和另一条数据线将接收的电流反馈到输出电路。 随后，输出电路将反馈的直流电流提供给选通线之一。 作为响应，输入电路通过另一对端子电阻器和另一个选通线路将接收到的电流再次反馈到输出电路。 然后将反馈电流排到地面。 因此，与以相同的电流量驱动数据和选通线对相比，电流消耗可以减半。 以这种方式，本发明可应用于当通过以所提供的电流驱动的多个数据总线对以高速传输数据时，减少电流消耗。

    Semiconductor memory
    6.
    发明授权
    Semiconductor memory 失效
    半导体存储器

    公开(公告)号：US6009024A

    公开(公告)日：1999-12-28

    申请号：US46880

    申请日：1998-03-24

    申请人： Takashi Hirata ,  Hiroyuki Yamauchi ,  Hironori Akamatsu ,  Keiichi Kusumoto ,  Toru Iwata ,  Satoshi Takahashi ,  Yutaka Terada

    发明人： Takashi Hirata ,  Hiroyuki Yamauchi ,  Hironori Akamatsu ,  Keiichi Kusumoto ,  Toru Iwata ,  Satoshi Takahashi ,  Yutaka Terada

    IPC分类号： G11C7/06 ,  G11C7/00

    CPC分类号： G11C7/06

    摘要： A semiconductor memory of the present invention includes: a plurality of memory cells; a pair of local bit lines connected to the plurality of memory cells; a local sense amplifier for amplifying a potential difference between the pair of local bit lines; a pair of global bit lines electrically connected to the pair of local bit lines through a switch; and a global sense amplifier for amplifying a potential difference between the pair of global bit lines, wherein the local sense amplifier includes a plurality of transistors, each of the plurality of transistors included in the local sense amplifier is a transistor of a first conductivity type, and the global sense amplifier includes a transistor of a second conductivity type different from the first conductivity type.

    摘要翻译： 本发明的半导体存储器包括：多个存储单元; 连接到所述多个存储器单元的一对局部位线; 本地读出放大器，用于放大一对局部位线之间的电位差; 一对全局位线通过开关电连接到该对局部位线; 以及用于放大所述一对全局位线之间的电位差的全局读出放大器，其中所述局部读出放大器包括多个晶体管，所述局部读出放大器中包括的所述多个晶体管中的每一个是第一导电类型的晶体管， 并且全球感测放大器包括不同于第一导电类型的第二导电类型的晶体管。

    Memory access buffer and reordering apparatus using priorities
    8.
    发明授权
    Memory access buffer and reordering apparatus using priorities 失效
    使用优先级的存储器访问缓冲器和重新排序装置

    公开(公告)号：US6145065A

    公开(公告)日：2000-11-07

    申请号：US67899

    申请日：1998-04-29

    申请人： Satoshi Takahashi ,  Hiroyuki Yamauchi ,  Hironori Akamatsu ,  Keiichi Kusumoto ,  Toru Iwata ,  Yutaka Terada ,  Takashi Hirata

    发明人： Satoshi Takahashi ,  Hiroyuki Yamauchi ,  Hironori Akamatsu ,  Keiichi Kusumoto ,  Toru Iwata ,  Yutaka Terada ,  Takashi Hirata

    IPC分类号： G06F13/16 ,  G06F12/02

    CPC分类号： G06F13/1631

    摘要： A current problem is that when a DRAM is to be accessed through a data bus, the DRAM is accessed independently of a bank, a row address, etc., and therefore, is inefficient. To solve this problem, an address bus and a data bus are connected to a main memory part independently of each other, a temporary memory part for holding a plurality of addresses in advance is disposed on the address bus side and holds addresses for every access to the main memory part regardless of transfer of data, thereby pipelining address inputting cycles. Further, for the purpose of an effective operation of the main memory part, using the addresses which are held, the addresses are rearranged in such a manner that addresses with the same row addresses become continuous to each other, or when there are not addresses with the same row addresses, addresses different banks from each other become continuous to each other, and the memory is thereafter accessed. This reduces the number of precharges, shortens a standby period which is necessary for a precharge, and realizes accessing while reducing a wasteful use of time.

    摘要翻译： 目前的问题在于，当通过数据总线访问DRAM时，独立于存储体，行地址等访问DRAM，因此是低效的。 为了解决这个问题，地址总线和数据总线彼此独立地连接到主存储器部分，预先存储多个地址的临时存储器部分设置在地址总线侧，并且保存地址以进行每次访问 主存储部分不管数据传输，从而流水线地址输入周期。 此外，为了主存储器部分的有效操作，使用所保存的地址，地址被重新排列，使得具有相同行地址的地址彼此连续，或者当没有地址与 相同的行地址，彼此不同的存储体彼此变得连续，并且此后访问存储器。 这减少了预充电次数，缩短了预充电所需的待机时间，并实现了访问，同时减少了浪费时间的使用。

    Data holding circuit
    10.
    发明授权
    Data holding circuit 失效
    数据保持电路

    公开(公告)号：US5757702A

    公开(公告)日：1998-05-26

    申请号：US739363

    申请日：1996-10-29

    申请人： Toru Iwata ,  Hironori Akamatsu ,  Hiroyuki Yamauchi

    发明人： Toru Iwata ,  Hironori Akamatsu ,  Hiroyuki Yamauchi

    IPC分类号： G11C11/412 ,  G11C11/419 ,  G11C7/00

    CPC分类号： G11C11/419 ,  G11C11/412

    摘要： A memory cell includes a first inverter and a second inverter connected with each other through the output node of one of the inverters and the input node of the other inverter, and first and second transistors. Each of the transistors connected with a word line at its gate electrode is interposed between one of a bit line pair and each memory node. This data holding circuit includes an element for increasing a memory cell supply potential for driving the pair of inverters to be higher than a supply potential applied to peripheral circuits, or an element for decreasing a ground voltage for driving the pair of inverters to be lower than a ground voltage applied to the peripheral circuits.

    摘要翻译： 存储单元包括通过其中一个反相器的输出节点和另一个反相器的输入节点以及第一和第二晶体管彼此连接的第一反相器和第二反相器。 在其栅电极处与字线连接的晶体管中的每一个插入在位线对和每个存储器节点之一之间。 该数据保持电路包括用于将用于驱动该对反相器的存储单元电源电位增加到高于施加到外围电路的电源电位的元件，或者用于将用于驱动该对反相器的接地电压降低到低于 施加到外围电路的接地电压。