公开(公告)号：US20120287699A1

公开(公告)日：2012-11-15

申请号：US13355781

申请日：2012-01-23

Applicant: Tae Sik YUN ,  Kang Seol LEE

Inventor： Tae Sik YUN ,  Kang Seol LEE

IPC: G11C11/24 ,  G11C7/12 ,  G11C7/06

CPC classification number: G11C11/4076 ,  G11C11/4091 ,  G11C11/4099

Abstract: A semiconductor memory device selects one of a plurality of memory cells as a dummy memory cell. The dummy memory cell is connected to a bit line that is complementary to a bit line connected to a selected memory cell. This technique advantageously compensates capacitance of the bit line. The semiconductor memory device comprises a selected memory cell connected to a first bit line and a first word line, a dummy memory cell connected to a second bit line complementary to the first bit line and a second word line, and a sense amplifier connected to the first and second bit lines and configured to read data stored in the selected memory cell by simultaneously enablement of the first and second word lines.

Abstract translation: 半导体存储器件选择多个存储单元中的一个作为虚拟存储单元。 虚拟存储器单元连接到与连接到所选存储单元的位线互补的位线。 该技术有利地补偿位线的电容。 半导体存储器件包括连接到第一位线和第一字线的选定存储器单元，连接到与第一位线互补的第二位线和第二字线的虚拟存储器单元，以及连接到第一位线的读出放大器 第一和第二位线，并且被配置为通过同时启用第一和第二字线来读取存储在所选存储单元中的数据。

公开(公告)号：US20120218843A1

公开(公告)日：2012-08-30

申请号：US13406117

申请日：2012-02-27

Applicant: Tae Sik YUN ,  Kang Seol LEE

Inventor： Tae Sik YUN ,  Kang Seol LEE

IPC: G11C11/406 ,  G11C7/22

CPC classification number: G11C11/40618 ,  G11C29/783

Abstract: Provided is a semiconductor device which performs a refresh operation by sequentially counting a refresh address including a main word line address, a mat address, and a sub word line address in order of the main word line address, the mat address, and the sub word line address. The semiconductor device includes a control signal generation unit configured to activate, latch, and output a toggle control signal when a delayed refresh signal is inputted at the initial stage, deactivate and output the toggle control signal after additionally counting a redundancy word line address when counting of the main word line address with respect to the mat address is completed, and then activate, latch, and output the toggle control signal when the delayed refresh signal is inputted.

Abstract translation: 提供一种半导体器件，其通过按照主字线地址，子地址和子字的顺序依次计数包括主字线地址，字地址和子字线地址的刷新地址来执行刷新操作 行地址。 该半导体装置包括：控制信号生成单元，被配置为当在初始阶段输入延迟的刷新信号时激活，锁存和输出触发控制信号，在对计数后的冗余字线地址进行额外计数之后停用并输出触发控制信号 完成相对于地址地址的主字线地址，然后当延迟刷新信号被输入时，激活，锁存和输出触发控制信号。

公开(公告)号：US20120188836A1

公开(公告)日：2012-07-26

申请号：US13356771

申请日：2012-01-24

Applicant: Kang Seol LEE ,  Tae Sik YUN

Inventor： Kang Seol LEE ,  Tae Sik YUN

IPC: G11C7/12 ,  G11C7/06

CPC classification number: G11C11/4091 ,  G11C11/4094

Abstract: A semiconductor memory apparatus includes a bit line sense amplifier unit and a driving voltage supply unit. The bit line sense amplifier unit senses and amplifies a signal provided from a memory cell using a pull-up driving voltage provided through a pull-up power line and a pull-down driving voltage provided through a pull-down power line. The driving voltage supply unit supplies the pull-down driving voltage having a first pull-down driving force during a first amplification period, and supplies the pull-down driving voltage having a second pull-down driving force greater than the first pull-down driving force during a second amplification period after the first amplification period.

Abstract translation: 半导体存储装置包括位线读出放大器单元和驱动电压提供单元。 位线读出放大器单元使用通过上拉电源线提供的上拉驱动电压和通过下拉电力线提供的下拉驱动电压来感测和放大从存储单元提供的信号。 驱动电压供应单元在第一放大期间提供具有第一下拉驱动力的下拉驱动电压，并且提供具有大于第一下拉驱动的第二下拉驱动力的下拉驱动电压 在第一扩增期后的第二扩增期间的力。

公开(公告)号：US20130234765A1

公开(公告)日：2013-09-12

申请号：US13602270

申请日：2012-09-03

Applicant: Kang Seol LEE ,  Jae Hyuk IM

Inventor： Kang Seol LEE ,  Jae Hyuk IM

IPC: H03L5/00

CPC classification number: G11C5/14 ,  G11C5/145 ,  G11C11/4074 ,  H03L5/00

Abstract: A voltage generation circuit of a semiconductor memory apparatus includes a plurality of pumping units configured to provide voltages to an output node; a sensing unit configured to sense a voltage level of the output node and generate a pumping enable signal; an oscillator configured to generate an oscillator signal in response to the pumping enable signal; and a control unit configured to selectively output the oscillator signal to the plurality of pumping units in response to an active signal, a power-up signal and a mode register set signal.

Abstract translation: 半导体存储装置的电压产生电路包括被配置为向输出节点提供电压的多个泵送单元; 感测单元，被配置为感测所述输出节点的电压电平并产生泵送使能信号; 配置为响应于所述泵浦使能信号产生振荡器信号的振荡器; 以及控制单元，被配置为响应于有效信号，上电信号和模式寄存器设置信号而选择性地将振荡器信号输出到多个泵浦单元。

公开(公告)号：US20090066314A1

公开(公告)日：2009-03-12

申请号：US12198562

申请日：2008-08-26

Applicant: Kang Seol LEE

Inventor： Kang Seol LEE

IPC: G05F3/16 ,  G06F17/50

CPC classification number: G05F3/267 ,  G06F17/5068

Abstract: A semiconductor device and a layout method of the same reduce a mismatch in a semiconductor device. The semiconductor device includes a first transistor unit providing a first path of current and a second transistor unit designed in a mirror structure to the first transistor unit and providing a second path of current. The layout of the second transistor unit has a shape identical to the first transistor unit and shifted in a first direction. The layout of the semiconductor device reduces a mismatch of the transistors occurring when masks are combined, and thereby reduces their offset.

Abstract translation: 半导体器件及其布置方法减少半导体器件中的失配。 该半导体器件包括提供电流的第一路径的第一晶体管单元和以第一晶体管单元的镜结构设计并提供第二电流路径的第二晶体管单元。 第二晶体管单元的布局具有与第一晶体管单元相同的形状并沿第一方向移位。 半导体器件的布局减少了当掩模组合时发生的晶体管的失配，从而减小它们的偏移。

公开(公告)号：US20110291639A1

公开(公告)日：2011-12-01

申请号：US12947441

申请日：2010-11-16

Applicant: Kang Seol LEE ,  Jae Hyuk Im

Inventor： Kang Seol LEE ,  Jae Hyuk Im

IPC: G05F3/16

CPC classification number: H03K19/00384

Abstract: A semiconductor integrated circuit includes an internal reference voltage generation unit configured to generate an internal reference voltage; a high voltage generation unit configured to pump an external driving voltage based on the internal reference voltage applied from the internal reference voltage generation unit, and generate a high voltage having a specified level; and a reference voltage transfer unit configured to generate a test reference voltage from a reference voltage in a package test mode to correspond to a change in a driving operation of the external driving voltage applied from outside, and monitor and force the internal reference voltage.

Abstract translation: 半导体集成电路包括：内部参考电压生成单元，被配置为产生内部参考电压; 高电压产生单元，被配置为基于从内部参考电压产生单元施加的内部参考电压来泵浦外部驱动电压，并产生具有指定电平的高电压; 以及参考电压传送单元，被配置为在封装测试模式下从参考电压产生测试参考电压，以对应于从外部施加的外部驱动电压的驱动操作的变化，并监视和强制内部参考电压。