利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

3 条记录 (耗时 0.027 秒)

    SEMICONDUCTOR MEMORY DEVICE AND MEMORY SYSTEM INCLUDING SAME
    1.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE AND MEMORY SYSTEM INCLUDING SAME 有权
    半导体存储器件和包括其的存储器系统

    公开(公告)号：US20160163377A1

    公开(公告)日：2016-06-09

    申请号：US14959003

    申请日：2015-12-04

    申请人： Tae Young OH ,  Su Yeon DOO ,  Seung Hoon OH ,  Jong Ho LEE ,  Kwang Il PARK

    发明人： Tae Young OH ,  Su Yeon DOO ,  Seung Hoon OH ,  Jong Ho LEE ,  Kwang Il PARK

    IPC分类号： G11C11/406 ,  G11C11/4091 ,  G11C11/408

    CPC分类号： G11C11/40615 ,  G11C11/40618

    摘要： A method of operating a semiconductor memory device is provided as follows. The semiconductor memory device receive a bank address for a first bank including a first word line, a second word line and a third word line. The semiconductor memory device receive a first row address to activate the first world line for a read operation or a write operation. The semiconductor memory device generates a second row address to refresh a plurality of memory cells associated with the second word line.

    摘要翻译： 如下提供操作半导体存储器件的方法。 半导体存储器件接收包括第一字线，第二字线和第三字线的第一存储体的存储体地址。 半导体存储器件接收第一行地址以激活用于读取操作或写入操作的第一世界线。 半导体存储器件产生第二行地址以刷新与第二字线相关联的多个存储单元。

    APPARATUS AND METHOD FOR PHASE LOCKED LOOP
    2.
    发明申请
    APPARATUS AND METHOD FOR PHASE LOCKED LOOP 审中-公开
    相位锁定环的装置和方法

    公开(公告)号：US20090129525A1

    公开(公告)日：2009-05-21

    申请号：US11945821

    申请日：2007-11-27

    申请人： Tae Young OH

    发明人： Tae Young OH

    IPC分类号： H03D3/24

    CPC分类号： H03D13/001

    摘要： The PLL (Phase Locked Loop) apparatus and the PLL method are disclosed, wherein an output clock signal is counted in response to a reference clock signal to detect a frequency offset value and divide the output clock signal by a prescribed value to generate a phase detection value in response to the reference clock signal, generating a frequency error value to adjust a frequency of the output clock signal if the frequency offset value is not between a prescribed frequency offset maximum value and a predetermined frequency offset minimum value, and generating a phase error value in response to the phase detection value to adjust a phase of the output clock signal if the frequency offset value is in between a prescribed frequency offset maximum value and a prescribed frequency offset minimum value.

    摘要翻译： 公开了PLL（锁相环）装置和PLL方法，其中响应于参考时钟信号对输出时钟信号进行计数，以检测频率偏移值，并将输出时钟信号除以规定值以产生相位检测 响应于参考时钟信号产生频率误差值，如果频率偏移值不在规定的频率偏移最大值和预定频率偏移最小值之间，则产生频率误差值以调整输出时钟信号的频率，并且产生相位误差 如果频率偏移值在规定的频率偏移最大值和规定的频率偏移最小值之间，则响应于相位检测值的值来调整输出时钟信号的相位。