公开(公告)号：US20190165769A1

公开(公告)日：2019-05-30

申请号：US15826910

申请日：2017-11-30

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Tsung-Hsien TSAI ,  Chen-Hsiang Hsieh ,  Ruey-Bin SHEEN ,  Chih-Hsien CHANG

IPC分类号： H03K3/03 ,  H03K3/356 ,  H03L7/099 ,  H03L7/087 ,  H03L7/081

摘要： A realignment ring-cell circuit is disclosed. The circuit includes a single-to-differential unit, an OR gate, an AND gate, a first P-type metal-oxide-semiconductor transistor, and a first N-type metal-oxide-semiconductor transistor. The single-to-differential unit has an input configured to receive a realignment signal, a first output for outputting a first differential output and a second output for outputting a second differential output. The first output for outputting is a first input to the OR gate. The second output for outputting is a first input to the AND gate. A gate of the P-type metal-oxide-semiconductor transistor is electrically connected to an output of the OR gate. A gate of the N-type metal-oxide-semiconductor transistor is electrically connected to an output of the AND gate. A drain of the P-type metal-oxide-semiconductor transistor and a drain of the N-type metal-oxide-semiconductor transistor are electrically connected to each other and are further electrically connected to a second input of the OR gate and a second input of the AND gate.

公开(公告)号：US10461723B2

公开(公告)日：2019-10-29

申请号：US15826910

申请日：2017-11-30

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Tsung-Hsien Tsai ,  Chen-Hsiang Hsieh ,  Ruey-Bin Sheen ,  Chih-Hsien Chang

IPC分类号： H03K3/03 ,  H03K3/356 ,  H03L7/081 ,  H03L7/087 ,  H03L7/099

摘要： A realignment ring-cell circuit is disclosed. The circuit includes a single-to-differential unit, an OR gate, an AND gate, a first P-type metal-oxide-semiconductor transistor, and a first N-type metal-oxide-semiconductor transistor. The single-to-differential unit has an input configured to receive a realignment signal, a first output for outputting a first differential output and a second output for outputting a second differential output. The first output for outputting is a first input to the OR gate. The second output for outputting is a first input to the AND gate. A gate of the P-type metal-oxide-semiconductor transistor is electrically connected to an output of the OR gate. A gate of the N-type metal-oxide-semiconductor transistor is electrically connected to an output of the AND gate. A drain of the P-type metal-oxide-semiconductor transistor and a drain of the N-type metal-oxide-semiconductor transistor are electrically connected to each other and are further electrically connected to a second input of the OR gate and a second input of the AND gate.