公开(公告)号：US20210375819A1

公开(公告)日：2021-12-02

申请号：US17074107

申请日：2020-10-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Fa Chen ,  Cheng-Feng Chen ,  Sung-Feng Yeh ,  Chuan-An Cheng

IPC: H01L23/00 ,  H01L25/065 ,  H01L25/00 ,  H01L21/78

Abstract: In a method, a wafer is bonded to a first carrier. The wafer includes a semiconductor substrate, and a first plurality of through-vias extending into the semiconductor substrate. The method further includes bonding a plurality of chips over the wafer, with gaps located between the plurality of chips, performing a gap-filling process to form gap-filling regions in the gaps, bonding a second carrier onto the plurality of chips and the gap-filling regions, de-bonding the first carrier from the wafer, and forming electrical connectors electrically connecting to conductive features in the wafer. The electrical connectors are electrically connected to the plurality of chips through the first plurality of through-vias.

公开(公告)号：US11721663B2

公开(公告)日：2023-08-08

申请号：US17074107

申请日：2020-10-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Fa Chen ,  Cheng-Feng Chen ,  Sung-Feng Yeh ,  Chuan-An Cheng

IPC: H01L23/28 ,  H01L23/367 ,  H01L25/065 ,  H01L23/00 ,  H01L25/00 ,  H01L21/78

CPC classification number: H01L24/80 ,  H01L21/78 ,  H01L24/08 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/08145 ,  H01L2224/80006 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2225/06541

Abstract: In a method, a wafer is bonded to a first carrier. The wafer includes a semiconductor substrate, and a first plurality of through-vias extending into the semiconductor substrate. The method further includes bonding a plurality of chips over the wafer, with gaps located between the plurality of chips, performing a gap-filling process to form gap-filling regions in the gaps, bonding a second carrier onto the plurality of chips and the gap-filling regions, de-bonding the first carrier from the wafer, and forming electrical connectors electrically connecting to conductive features in the wafer. The electrical connectors are electrically connected to the plurality of chips through the first plurality of through-vias.

公开(公告)号：US20230352439A1

公开(公告)日：2023-11-02

申请号：US18338107

申请日：2023-06-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Fa Chen ,  Cheng-Feng Chen ,  Sung-Feng Yeh ,  Chuan-An Cheng

IPC: H01L23/00 ,  H01L25/065 ,  H01L25/00 ,  H01L21/78

CPC classification number: H01L24/80 ,  H01L25/0657 ,  H01L24/08 ,  H01L25/50 ,  H01L21/78 ,  H01L2224/80896 ,  H01L2225/06541 ,  H01L2224/08145 ,  H01L2224/80006 ,  H01L2224/80895

Abstract: In a method, a wafer is bonded to a first carrier. The wafer includes a semiconductor substrate, and a first plurality of through-vias extending into the semiconductor substrate. The method further includes bonding a plurality of chips over the wafer, with gaps located between the plurality of chips, performing a gap-filling process to form gap-filling regions in the gaps, bonding a second carrier onto the plurality of chips and the gap-filling regions, de-bonding the first carrier from the wafer, and forming electrical connectors electrically connecting to conductive features in the wafer. The electrical connectors are electrically connected to the plurality of chips through the first plurality of through-vias.

公开(公告)号：US20240379614A1

公开(公告)日：2024-11-14

申请号：US18782253

申请日：2024-07-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Fa Chen ,  Cheng-Feng Chen ,  Sung-Feng Yeh ,  Chuan-An Cheng

IPC: H01L23/00 ,  H01L21/78 ,  H01L25/00 ,  H01L25/065

Abstract: In a method, a wafer is bonded to a first carrier. The wafer includes a semiconductor substrate, and a first plurality of through-vias extending into the semiconductor substrate. The method further includes bonding a plurality of chips over the wafer, with gaps located between the plurality of chips, performing a gap-filling process to form gap-filling regions in the gaps, bonding a second carrier onto the plurality of chips and the gap-filling regions, de-bonding the first carrier from the wafer, and forming electrical connectors electrically connecting to conductive features in the wafer. The electrical connectors are electrically connected to the plurality of chips through the first plurality of through-vias.