公开(公告)号：US11653498B2

公开(公告)日：2023-05-16

申请号：US16035251

申请日：2018-07-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Gulbagh Singh ,  Chen-Hao Li ,  Chih-Ming Lee ,  Chi-Yen Lin ,  Cheng-Tsu Liu

IPC: H01L27/11568 ,  H01L29/423 ,  H01L21/28 ,  H01L29/792

CPC classification number: H01L27/11568 ,  H01L29/40117 ,  H01L29/42348 ,  H01L29/792

Abstract: The present disclosure relates to a memory device that includes a substrate and source and drain regions formed in the substrate. The memory device includes a gate dielectric formed on the substrate and between the source and drain regions. The memory device also includes a gate structure formed on the gate dielectric and the gate structure has a planar top surface. The memory device further includes a multi-spacer structure that includes first, second, and third spacers. The first spacer is formed on a sidewall of the gate structure and a top surface of one of the source and drain regions. The second spacer is formed on a sidewall of the first spacer and the second spacer has a dielectric constant greater than a dielectric constant of the first spacer. The third spacer is formed on a sidewall of the second spacer and a horizontal surface of the first spacer.