公开(公告)号：US20170317186A1

公开(公告)日：2017-11-02

申请号：US15651344

申请日：2017-07-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chao-Hsuing Chen ,  Ling-Sung Wang ,  Chi-Yen Lin

IPC: H01L29/66 ,  H01L29/165 ,  H01L29/16 ,  H01L29/04 ,  H01L21/02 ,  H01L21/306 ,  H01L21/265 ,  H01L29/78 ,  H01L29/08

CPC classification number: H01L29/66636 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/26506 ,  H01L21/30604 ,  H01L29/045 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/165 ,  H01L29/7848

Abstract: Some embodiments of the present disclosure relates to a method of forming a semiconductor device having a strained channel and an associated device. In some embodiments, the method includes performing a first etching process by selectively exposing a substrate to a first etchant to produce a recess defined by sidewalls and a bottom surface of the substrate. An implantation process is performed to form an etch stop layer along the bottom surface. A second etching process is performed by exposing the sidewalls and the bottom surface defining the recess to a second etchant to form a source/drain recess. The source/drain recess laterally extends past the etch stop layer in opposing directions. A semiconductor material is formed within the source/drain recess.

公开(公告)号：US20240112924A1

公开(公告)日：2024-04-04

申请号：US18150256

申请日：2023-01-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsu-Hsien Chen ,  Chen-Shien Chen ,  Ting Hao Kuo ,  Chi-Yen Lin ,  Yu-Chih Huang

IPC: H01L21/56 ,  H01L21/306 ,  H01L21/768 ,  H01L21/78 ,  H01L23/522 ,  H01L23/538

CPC classification number: H01L21/563 ,  H01L21/30604 ,  H01L21/76802 ,  H01L21/78 ,  H01L23/5226 ,  H01L23/5389

Abstract: An integrated circuit package including integrated circuit dies with slanted sidewalls and a method of forming are provided. The integrated circuit package may include a first integrated circuit die, a first gap-fill dielectric layer around the first integrated circuit die, a second integrated circuit die underneath the first integrated circuit die, and a second gap-fill dielectric layer around the second integrated circuit die. The first integrated circuit die may include a first substrate, wherein a first angle is between a first sidewall of the first substrate and a bottom surface of the first substrate, and a first interconnect structure on the bottom surface of the first substrate, wherein a second angle is between a first sidewall of the first interconnect structure and the bottom surface of the first substrate. The first angle may be larger than the second angle.

公开(公告)号：US11653498B2

公开(公告)日：2023-05-16

申请号：US16035251

申请日：2018-07-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Gulbagh Singh ,  Chen-Hao Li ,  Chih-Ming Lee ,  Chi-Yen Lin ,  Cheng-Tsu Liu

IPC: H01L27/11568 ,  H01L29/423 ,  H01L21/28 ,  H01L29/792

CPC classification number: H01L27/11568 ,  H01L29/40117 ,  H01L29/42348 ,  H01L29/792

Abstract: The present disclosure relates to a memory device that includes a substrate and source and drain regions formed in the substrate. The memory device includes a gate dielectric formed on the substrate and between the source and drain regions. The memory device also includes a gate structure formed on the gate dielectric and the gate structure has a planar top surface. The memory device further includes a multi-spacer structure that includes first, second, and third spacers. The first spacer is formed on a sidewall of the gate structure and a top surface of one of the source and drain regions. The second spacer is formed on a sidewall of the first spacer and the second spacer has a dielectric constant greater than a dielectric constant of the first spacer. The third spacer is formed on a sidewall of the second spacer and a horizontal surface of the first spacer.

公开(公告)号：US11101354B2

公开(公告)日：2021-08-24

申请号：US16983369

申请日：2020-08-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Gulbagh Singh ,  Cheng-Yeh Huang ,  Chin-Nan Chang ,  Chih-Ming Lee ,  Chi-Yen Lin

IPC: H01L29/40 ,  H01L21/762 ,  H01L21/768 ,  H01L21/324 ,  H01L29/45 ,  H01L21/265

Abstract: A method for forming a semiconductor device structure is provided. The method includes providing a semiconductor substrate. The method includes forming an isolation structure in the semiconductor substrate. The isolation structure surrounds a first active region of the semiconductor substrate. The method includes forming a semiconductor strip structure over the semiconductor substrate. The semiconductor strip structure extends across the first active region and extends over the isolation structure, the semiconductor strip structure has a first doped region and a spacing region connected to the first doped region, the first doped region extends across the first active region, the spacing region is over the isolation structure, and the spacing region is an undoped region. The method includes performing an implantation process over the spacing region. The method includes forming a metal silicide layer over the semiconductor strip structure to continuously cover the first doped region and the spacing region.

公开(公告)号：US09337126B2

公开(公告)日：2016-05-10

申请号：US14091610

申请日：2013-11-27

Applicant: Taiwan Semiconductor Manufacturing CO., LTD.

Inventor： Chen-Hao Li ,  Ying-Han Chiou ,  Chi-Yen Lin

IPC: H01L23/48 ,  H01L21/768 ,  H01L23/00

CPC classification number: H01L23/481 ,  H01L21/76838 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/03462 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05684 ,  H01L2224/13022 ,  H01L2224/13025 ,  H01L2224/16235 ,  H01L2224/16238 ,  H01L2224/81193 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/37001 ,  H01L2924/00014

Abstract: An integrated circuit and a method of fabricating the integrated circuit are provided. In various embodiments, the integrated circuit includes a first substrate, a second substrate, and a bump pad. The first substrate has at least one active device and a plurality of first metallic pads electrically connected to the active device. The first substrate has front-end-of-line processing layers without back-end-of-line processing layers over the front-end-of-line processing layers. The second substrate has a semiconductor substrate and an interconnect structure disposed on the semiconductor substrate, and the interconnect structure has at least one second metallic pad. The second substrate does not include any active devices. The bump pad is sandwiched by the first substrate and the second substrate. The active device and the first metallic pad of the first substrate are electrically connected to the second metallic pad of the second substrate through the bump pad.

Abstract translation: 提供集成电路和制造集成电路的方法。 在各种实施例中，集成电路包括第一衬底，第二衬底和凸块焊盘。 第一基板具有至少一个有源器件和电连接到有源器件的多个第一金属焊盘。 第一衬底具有在行前处理层之上没有后端行处理层的前端处理层。 第二衬底具有设置在半导体衬底上的半导体衬底和互连结构，并且互连结构具有至少一个第二金属衬垫。 第二基板不包括任何有源器件。 凸块由第一基板和第二基板夹持。 第一基板的有源器件和第一金属焊盘通过凸块焊接电连接到第二衬底的第二金属焊盘。

公开(公告)号：US20150145119A1

公开(公告)日：2015-05-28

申请号：US14091610

申请日：2013-11-27

Applicant: Taiwan Semiconductor Manufacturing CO., LTD.

Inventor： Chen-Hao Li ,  Ying-Han Chiou ,  Chi-Yen Lin

IPC: H01L23/48 ,  H01L23/00 ,  H01L21/768

CPC classification number: H01L23/481 ,  H01L21/76838 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/03462 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05684 ,  H01L2224/13022 ,  H01L2224/13025 ,  H01L2224/16235 ,  H01L2224/16238 ,  H01L2224/81193 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/37001 ,  H01L2924/00014

Abstract: An integrated circuit and a method of fabricating the integrated circuit are provided. In various embodiments, the integrated circuit includes a first substrate, a second substrate, and a bump pad. The first substrate has at least one active device and a plurality of first metallic pads electrically connected to the active device. The first substrate has front-end-of-line processing layers without back-end-of-line processing layers over the front-end-of-line processing layers. The second substrate has a semiconductor substrate and an interconnect structure disposed on the semiconductor substrate, and the interconnect structure has at least one second metallic pad. The second substrate does not include any active devices. The bump pad is sandwiched by the first substrate and the second substrate. The active device and the first metallic pad of the first substrate are electrically connected to the second metallic pad of the second substrate through the bump pad.

Abstract translation: 提供集成电路和制造集成电路的方法。 在各种实施例中，集成电路包括第一衬底，第二衬底和凸块焊盘。 第一基板具有至少一个有源器件和电连接到有源器件的多个第一金属焊盘。 第一衬底具有在行前处理层之上没有后端行处理层的前端处理层。 第二衬底具有设置在半导体衬底上的半导体衬底和互连结构，并且互连结构具有至少一个第二金属衬垫。 第二基板不包括任何有源器件。 凸块由第一基板和第二基板夹持。 第一基板的有源器件和第一金属焊盘通过凸块焊接电连接到第二衬底的第二金属焊盘。

公开(公告)号：US20250062201A1

公开(公告)日：2025-02-20

申请号：US18501254

申请日：2023-11-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Shien Chen ,  Chi-Yen Lin ,  Po-Chen Chen ,  Wu-An Weng ,  Hsu-Hsien Chen

IPC: H01L23/498 ,  H01L21/02 ,  H01L21/683 ,  H01L23/00 ,  H01L25/065

Abstract: A package includes a first integrated circuit die and a second integrated circuit die over and bonded to the first integrated circuit die. A first surface region of the second integrated circuit die is hydrophobic, and the first integrated circuit die and the second integrated circuit die are bonded together with dielectric-to-dielectric bonds and metal-to-metal bonds. The package further includes a first insulating material over the first integrated circuit and surrounding the second integrated circuit die. The first insulating material contacts the first surface region.

公开(公告)号：US10748911B2

公开(公告)日：2020-08-18

申请号：US16020855

申请日：2018-06-27

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Gulbagh Singh ,  Shun-Chi Tsai ,  Chih-Ming Lee ,  Chi-Yen Lin ,  Kuo-Hung Lo

IPC: H01L27/11 ,  H01L29/423 ,  H01L29/06 ,  H01L21/8234 ,  G11C11/412 ,  H01L27/02

Abstract: An integrated circuit structure includes a semiconductor substrate, an active area, a gate electrode, and a butted contact. The active area is oriented in a first direction and has at least one tooth portion extending in a second direction in the semiconductor substrate. The gate electrode overlies the active area and extends in the second direction. The butted contact has a first portion above the gate electrode and a second portion above the active area. A portion of the second portion of the butted contact lands on the tooth portion.

公开(公告)号：US09735252B2

公开(公告)日：2017-08-15

申请号：US15151663

申请日：2016-05-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chao-Hsuing Chen ,  Ling-Sung Wang ,  Chi-Yen Lin

IPC: H01L29/66 ,  H01L29/165 ,  H01L29/78 ,  H01L29/04 ,  H01L29/08 ,  H01L21/02 ,  H01L21/265 ,  H01L21/306 ,  H01L29/16

CPC classification number: H01L29/66636 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/26506 ,  H01L21/30604 ,  H01L29/045 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/165 ,  H01L29/7848

Abstract: Some embodiments of the present disclosure relates to a method of forming a transistor device having a strained channel and an associated device. In some embodiments, the method is performed by performing a first etch of a substrate to produce a recess having a largest width at an opening along a top surface of the substrate. An etch stop layer is formed by doping a bottom surface of the recess with a dopant. A second etch of the recess is then performed to form a source/drain recess, wherein the etch stop layer resists etching of the second etch. A stress inducing material is formed within the source/drain recess onto the etch stop layer.

公开(公告)号：US09196545B2

公开(公告)日：2015-11-24

申请号：US14305427

申请日：2014-06-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chao-Hsuing Chen ,  Ling-Sung Wang ,  Chi-Yen Lin

IPC: H01L21/8238 ,  H01L27/088 ,  H01L27/11 ,  H01L27/02 ,  H01L21/768 ,  H01L29/78 ,  H01L29/06 ,  H01L29/165 ,  H01L21/8234

CPC classification number: H01L21/823814 ,  H01L21/76895 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823475 ,  H01L21/823878 ,  H01L27/0207 ,  H01L27/088 ,  H01L27/1104 ,  H01L29/0688 ,  H01L29/165 ,  H01L29/7848

Abstract: The present disclosure relates to a method for fabricating a butted a contact arrangement configured to couple two transistors, wherein an active region of a first transistor is coupled to a gate of a second transistor. The gate of the second transistor is formed from a gate material which comprises a dummy gate of the first transistor, and is configured to straddle a boundary between the active region of the first transistor and an isolation layer formed about the first transistor. The butted a contact arrangement results in a decreased contact resistance for the butted contact as compared to previous methods.

Abstract translation: 本公开涉及一种用于制造对接的配置成耦合两个晶体管的接触装置的方法，其中第一晶体管的有源区耦合到第二晶体管的栅极。 第二晶体管的栅极由包括第一晶体管的伪栅极的栅极材料形成，并且被配置为跨越第一晶体管的有源区域和围绕第一晶体管形成的隔离层之间的边界。 与之前的方法相比，对接的接触布置导致对接触点的接触电阻降低。