公开(公告)号：US20200091039A1

公开(公告)日：2020-03-19

申请号：US16373915

申请日：2019-04-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tung-Liang SHAO ,  Wen-Lin SHIH ,  Su-Chun YANG ,  Chih-Hang TUNG ,  Chen-Hua YU

IPC: H01L23/48 ,  H01L21/768 ,  H01L23/00 ,  H01L23/522 ,  H01L23/528 ,  H01L25/00

Abstract: A package structure and method for forming the same are provided. The package structure includes a first interconnect structure formed over a first substrate, and the first interconnect structure includes a first metal layer. The package structure further includes a second interconnect structure formed over a second substrate. The package structure includes a bonding structure between the first interconnect structure and the second interconnect structure. The bonding structure includes a first intermetallic compound (IMC) and a second intermetallic compound (IMC), a portion of the first IMC protrudes from the sidewall surfaces of the second IMC, and there could be a grain boundary between the first IMC and the second IMC.

公开(公告)号：US20200091034A1

公开(公告)日：2020-03-19

申请号：US16419672

申请日：2019-05-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tung-Liang SHAO ,  Jen-Yu WANG ,  Chung-Jung WU ,  Chih-Hang TUNG ,  Chen-Hua YU

IPC: H01L23/42 ,  H01L23/00 ,  H01L23/31 ,  H01L21/56 ,  H01L25/18

Abstract: A semiconductor package is provided. The semiconductor package includes a substrate and a semiconductor die over the substrate. A heat-dissipating feature covers the substrate and the semiconductor die, and a composite thermal interface material (TIM) structure is thermally bonded between the semiconductor die and the heat-dissipating feature. The composite TIM structure includes a metal-containing matrix material layer and polymer particles embedded in the metal-containing matrix material layer.

公开(公告)号：US20200058614A1

公开(公告)日：2020-02-20

申请号：US16373900

申请日：2019-04-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Hang TUNG ,  Tung-Liang SHAO ,  Su-Chun YANG ,  Geng-Ming CHANG ,  Chen-Hua YU

IPC: H01L23/00

Abstract: A method for forming a chip package structure is provided. The method includes partially removing a first redistribution layer to form an alignment trench in the first redistribution layer. The alignment trench surrounds a bonding portion of the first redistribution layer. The method includes forming a liquid layer over the bonding portion. The method includes disposing a chip structure over the liquid layer, wherein a first width of the bonding portion is substantially equal to a second width of the chip structure. The method includes evaporating the liquid layer. The chip structure is in direct contact with the bonding portion after the liquid layer is evaporated.

公开(公告)号：US20180012880A1

公开(公告)日：2018-01-11

申请号：US15205238

申请日：2016-07-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Su-Chun YANG ,  Yi-Li HSIAO ,  Tung-Liang SHAO ,  Chih-Hang TUNG ,  Chen-Hua YU

IPC: H01L25/00 ,  H01L25/065 ,  H01L25/18

CPC classification number: H01L25/50 ,  H01L21/30604 ,  H01L25/0652 ,  H01L2224/16145 ,  H01L2224/73204 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06537 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2225/06565 ,  H01L2225/06589 ,  H01L2924/18161

Abstract: Methods for forming a chip package are provided. The method includes providing at least one carrier substrate including first semiconductor dies mounted thereon. The method also includes forming a first noble metal layer including nanopores irregularly distributed therein to cover each one of the first semiconductor dies. The method further includes immersing the carrier substrate with the first semiconductor dies into an etchant solution including a fluoride etchant and an oxidizing agent, so that each one of the first semiconductor dies covered by the first noble metal layer is thinned.