公开(公告)号：US20170117253A1

公开(公告)日：2017-04-27

申请号：US14919378

申请日：2015-10-21

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chen-Hua YU ,  Ming-Fa CHEN ,  Sung-Feng YEH

IPC: H01L25/065 ,  H01L21/66

CPC classification number: H01L25/0657 ,  H01L21/568 ,  H01L21/76898 ,  H01L22/32 ,  H01L23/147 ,  H01L23/3114 ,  H01L23/3135 ,  H01L23/481 ,  H01L23/49811 ,  H01L23/5389 ,  H01L24/08 ,  H01L24/09 ,  H01L24/19 ,  H01L24/20 ,  H01L24/24 ,  H01L24/25 ,  H01L24/80 ,  H01L24/82 ,  H01L24/94 ,  H01L24/96 ,  H01L2224/04105 ,  H01L2224/05571 ,  H01L2224/08145 ,  H01L2224/08146 ,  H01L2224/08225 ,  H01L2224/09517 ,  H01L2224/12105 ,  H01L2224/16227 ,  H01L2224/24105 ,  H01L2224/24226 ,  H01L2224/25 ,  H01L2224/2518 ,  H01L2224/73267 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/80948 ,  H01L2224/82031 ,  H01L2224/821 ,  H01L2224/9222 ,  H01L2224/92244 ,  H01L2224/94 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2924/15311 ,  H01L2924/3511 ,  H01L2224/80 ,  H05K3/467 ,  H01L2224/80001 ,  H01L2224/82

Abstract: A chip package is provided. The chip package includes a semiconductor chip and a semiconductor die over the semiconductor chip. The chip package also includes a dielectric layer over the semiconductor chip and encapsulating the semiconductor die, and the dielectric layer is substantially made of a semiconductor oxide material. The chip package further includes a conductive feature penetrating through a semiconductor substrate of the semiconductor die and physically connecting a conductive pad of the semiconductor chip.

公开(公告)号：US20240079324A1

公开(公告)日：2024-03-07

申请号：US18503947

申请日：2023-11-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jie CHEN ,  Ying-Ju CHEN ,  Chen-Hua YU ,  Der-Chyang YEH ,  Hsien-Wei CHEN

IPC: H01L23/528 ,  H01L23/00 ,  H01L23/522 ,  H01L25/00 ,  H01L25/10

CPC classification number: H01L23/5283 ,  H01L23/5226 ,  H01L24/02 ,  H01L24/16 ,  H01L24/19 ,  H01L24/20 ,  H01L24/24 ,  H01L24/25 ,  H01L24/96 ,  H01L25/105 ,  H01L25/50 ,  H01L24/73 ,  H01L24/92 ,  H01L24/97 ,  H01L25/0657 ,  H01L2224/0233 ,  H01L2224/02373 ,  H01L2224/02375 ,  H01L2224/02379 ,  H01L2224/02381 ,  H01L2224/16235 ,  H01L2224/24147 ,  H01L2224/25171 ,  H01L2224/73209 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058

Abstract: A method of forming an integrated circuit (IC) package with improved performance and reliability is disclosed. The method includes forming a singulated IC die, coupling the singulated IC die to a carrier substrate, and forming a routing structure. The singulated IC die has a conductive via and the conductive via has a peripheral edge. The routing structure has a conductive structure coupled to the conductive via. The routing structure further includes a cap region overlapping an area of the conductive via, a routing region having a first width from a top-down view, and an intermediate region having a second width from the top-down view along the peripheral edge of the conductive via. The intermediate region is arranged to couple the cap region to the routing region and the second width is greater than the first width.

公开(公告)号：US20200091034A1

公开(公告)日：2020-03-19

申请号：US16419672

申请日：2019-05-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tung-Liang SHAO ,  Jen-Yu WANG ,  Chung-Jung WU ,  Chih-Hang TUNG ,  Chen-Hua YU

IPC: H01L23/42 ,  H01L23/00 ,  H01L23/31 ,  H01L21/56 ,  H01L25/18

Abstract: A semiconductor package is provided. The semiconductor package includes a substrate and a semiconductor die over the substrate. A heat-dissipating feature covers the substrate and the semiconductor die, and a composite thermal interface material (TIM) structure is thermally bonded between the semiconductor die and the heat-dissipating feature. The composite TIM structure includes a metal-containing matrix material layer and polymer particles embedded in the metal-containing matrix material layer.

公开(公告)号：US20190051635A1

公开(公告)日：2019-02-14

申请号：US16159816

申请日：2018-10-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua YU ,  An-Jhih SU ,  Jing-Cheng LIN ,  Po-Hao TSAI

IPC: H01L25/065 ,  H01L21/56 ,  H01L23/60 ,  H01L23/498 ,  H01L21/78 ,  H01L25/00 ,  H01L23/00 ,  H01L23/31

Abstract: A chip package structure is provided. The chip package structure includes a chip structure. The chip package structure includes a first ground bump below the chip structure. The chip package structure includes a conductive shielding film disposed over the chip structure and extending onto the first ground bump. The conductive shielding film is electrically connected to the first ground bump.

公开(公告)号：US20190020212A1

公开(公告)日：2019-01-17

申请号：US16132688

申请日：2018-09-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua YU ,  Hao-Yi TSAI ,  Tzu-Sung HUANG ,  Ming-Hung TSENG ,  Hung-Yi KUO

IPC: H02J7/02 ,  H01L21/3205 ,  H01L23/10 ,  H01L23/31 ,  H01L23/498 ,  H01L23/522 ,  H01L23/538 ,  H01L23/64

Abstract: A semiconductor device package is provided, including a semiconductor device, a magnetic flux generation unit, a molding material, and a conductive slot. The magnetic flux generation unit is surrounding an axis and configured to produce magnetic flux passes through the magnetic flux generation unit. The molding material is surrounding the semiconductor device and the magnetic flux generation unit. The conductive slot is positioned over the molding material, wherein an opening is formed on the conductive slot, and the axis passes through the opening.

公开(公告)号：US20180286776A1

公开(公告)日：2018-10-04

申请号：US15679027

申请日：2017-08-16

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chih-Hsuan TAI ,  Ting-Ting KUO ,  Yu-Chih HUANG ,  Chih-Hua CHEN ,  Hao-Yi TSAI ,  Chung-Shi LIU ,  Chen-Hua YU

IPC: H01L23/31 ,  H01L23/528 ,  H01L23/522 ,  H01L21/56 ,  H01L21/48

CPC classification number: H01L23/3128 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/561 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3135 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5389 ,  H01L24/13 ,  H01L2221/68359 ,  H01L2224/13147

Abstract: A package structure includes a semiconductor device, a first molding compound, a through-via, a first dielectric layer, a first redistribution line, and a second molding compound. The first molding compound is in contact with a sidewall of the semiconductor device. The through-via is in the first molding compound and is electrically connected to the semiconductor device. The first dielectric layer is over the semiconductor device. The first redistribution line is in the first dielectric layer and is electrically connected to the semiconductor device and the through-via. The second molding compound is in contact with a sidewall of the first dielectric layer.

公开(公告)号：US20180166405A1

公开(公告)日：2018-06-14

申请号：US15625678

申请日：2017-06-16

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO. LTD.

Inventor： Yung-Ping CHIANG ,  Nien-Fang WU ,  Min-Chien HSIAO ,  Yi-Che CHIANG ,  Chao-Wen SHIH ,  Shou-Zen CHANG ,  Chung-Shi LIU ,  Chen-Hua YU

IPC: H01L23/66 ,  H01L23/00 ,  H01L23/552 ,  H01L23/31 ,  H01L25/065 ,  H01L21/56

CPC classification number: H01L23/66 ,  H01L21/568 ,  H01L23/3121 ,  H01L23/5389 ,  H01L23/552 ,  H01L24/02 ,  H01L24/13 ,  H01L24/19 ,  H01L24/24 ,  H01L24/25 ,  H01L24/32 ,  H01L25/0655 ,  H01L2223/6644 ,  H01L2223/6677 ,  H01L2224/02331 ,  H01L2224/02371 ,  H01L2224/02379 ,  H01L2224/02381 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/13024 ,  H01L2224/24265 ,  H01L2224/25171 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19104 ,  H01L2924/3025 ,  H01L2224/83

Abstract: Structures and formation methods of a chip package are provided. The chip package includes a semiconductor die having a conductive element and a first protective layer surrounding the semiconductor die. The chip package also includes a second protective layer over the semiconductor die and the first protective layer. The chip package further includes an antenna element over the second protective layer. The antenna element is electrically connected to the conductive element of the semiconductor die.

公开(公告)号：US20170005072A1

公开(公告)日：2017-01-05

申请号：US15003150

申请日：2016-01-21

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Wen-Hsin WEI ,  Chi-Hsi WU ,  Chen-Hua YU ,  Hsien-Pin HU ,  Shang-Yun HOU ,  Wei-Ming CHEN

IPC: H01L25/065 ,  H01L23/00 ,  H01L21/3105 ,  H01L21/56 ,  H01L25/00 ,  H01L23/31 ,  H01L23/538

CPC classification number: H01L25/0652 ,  H01L21/486 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/5384 ,  H01L24/03 ,  H01L24/09 ,  H01L24/96 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/04105 ,  H01L2224/06181 ,  H01L2224/08235 ,  H01L2224/12105 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/17181 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73259 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/15311 ,  H01L2924/18161 ,  H01L2924/182

Abstract: Structures and formation methods of a chip package are provided. The chip package includes a chip stack including a number of semiconductor dies. The chip package also includes a semiconductor chip, and the semiconductor chip is higher than the chip stack. The chip package further includes a package layer covering a top and sidewalls of the chip stack and sidewalls of the semiconductor chip.

Abstract translation: 提供了芯片封装的结构和形成方法。 芯片封装包括包括多个半导体管芯的芯片堆叠。 芯片封装还包括半导体芯片，并且半导体芯片高于芯片堆叠。 芯片封装还包括覆盖芯片堆叠的顶部和侧壁以及半导体芯片的侧壁的封装层。

公开(公告)号：US20170005071A1

公开(公告)日：2017-01-05

申请号：US14981458

申请日：2015-12-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wen-Hsin WEI ,  Chi-Hsi WU ,  Chen-Hua YU ,  Hsien-Pin HU ,  Shang-Yun HOU ,  Wei-Ming CHEN

IPC: H01L25/065 ,  H01L21/48 ,  H01L25/00 ,  H01L21/56 ,  H01L23/31 ,  H01L23/498

CPC classification number: H01L25/0652 ,  H01L21/486 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49833 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H05K3/363

Abstract: Structures and formation methods of a chip package are provided. The chip package includes a first chip structure and a second chip structure. Heights of the first chip structure and the second chip structure are different. The chip package also includes a package layer covering sidewalls of the first chip structure and sidewalls of the second chip structure. Top surfaces of the first chip structure and the second chip structure are not covered by the package layer.

Abstract translation: 提供了芯片封装的结构和形成方法。 芯片封装包括第一芯片结构和第二芯片结构。 第一芯片结构和第二芯片结构的高度是不同的。 芯片封装还包括覆盖第一芯片结构的侧壁和第二芯片结构的侧壁的封装层。 第一芯片结构和第二芯片结构的顶表面不被封装层覆盖。

公开(公告)号：US20150011059A1

公开(公告)日：2015-01-08

申请号：US14497920

申请日：2014-09-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua YU ,  Liang-Gi YAO ,  Cheng-Tung LIN

IPC: H01L21/8238 ,  H01L29/51 ,  H01L29/49 ,  H01L21/265 ,  H01L21/28

CPC classification number: H01L21/823857 ,  H01L21/26566 ,  H01L21/28035 ,  H01L21/28158 ,  H01L21/823828 ,  H01L21/823842 ,  H01L29/4916 ,  H01L29/518

Abstract: A layer of P-metal material having a work function of about 4.3 or 4.4 eV or less is formed over a high-k dielectric layer. Portions of the N-metal layer are converted to P-metal materials by introducing additives such as O, C, N, Si or others to produce a P-metal material having an increased work function of about 4.7 or 4.8 eV or greater. A TaC film may be converted to a material of TaCO, TaCN, or TaCON using this technique. The layer of material including original N-metal portions and converted P-metal portions is then patterned using a single patterning operation to simultaneously form semiconductor devices from both the unconverted N-metal sections and converted P-metal sections.

Abstract translation: 在高k电介质层上形成功函数约4.3或4.4eV或更小的P金属材料层。 通过引入添加剂如O，C，N，Si等将N金属层的一部分转化为P金属材料，以产生具有约4.7或4.8eV或更大功函数的P金属材料。 使用这种技术可以将TaC膜转变为TaCO，TaCN或TaCON的材料。 然后使用单一图案化操作来构图包括原始N-金属部分和转换的P金属部分的材料层，以同时从未转换的N金属部分和转换的P金属部分形成半导体器件。