公开(公告)号：US09786569B1

公开(公告)日：2017-10-10

申请号：US15334912

申请日：2016-10-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-De Ho ,  Shu-Hong Lin ,  Ya Hui Chang ,  Chih-Jung Chiang ,  Chang-Yi Tsai ,  Tsung-Lin Yang ,  Kuei-Shun Chen

IPC: H01L21/00 ,  H01L21/66 ,  H01L23/544 ,  H01L21/027

CPC classification number: H01L22/20 ,  G03F7/70633 ,  H01L22/12 ,  H01L23/544 ,  H01L2223/54426 ,  H01L2223/54453

Abstract: A method includes receiving a device having a first layer and a second layer over the first layer, the first layer having a first overlay mark. The method further includes forming a first resist pattern over the second layer, the first resist pattern having a second overlay mark. The method further includes performing a first overlay measurement using the second overlay mark in the first resist pattern and the first overlay mark; and performing one or more first manufacturing processes, thereby transferring the second overlay mark into the second layer and removing the first resist pattern. The method further includes performing one or more second manufacturing processes that include forming a third layer over the second layer. After the performing of the one or more second manufacturing processes, the method includes performing a second overlay measurement using the second overlay mark in the second layer and the first overlay mark.