公开(公告)号：US20240290864A1

公开(公告)日：2024-08-29

申请号：US18463596

申请日：2023-09-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-De Ho ,  Szuya Liao

IPC: H01L29/66 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/423

CPC classification number: H01L29/66545 ,  H01L21/823412 ,  H01L21/823475 ,  H01L27/088 ,  H01L29/0649 ,  H01L29/0665 ,  H01L29/42392 ,  H01L29/66553

Abstract: A semiconductor device includes a backside gate etch stop layer (ESL) on a backside of a first gate stack, wherein a plurality of first nanostructures overlaps the backside gate ESL. The backside gate ESL may comprise a high-k dielectric material. The semiconductor device further includes the plurality of first nanostructures extending between first source/drain regions and a plurality of second nanostructures over the plurality of first nanostructures and extending between second source/drain regions. A first gate stack is disposed around the plurality of first nanostructures, and a second gate stack over the first gate stack is disposed around the plurality of second nanostructures. A backside gate contact extends through the backside gate ESL to be electrically coupled to the first gate stack.

公开(公告)号：US20240072115A1

公开(公告)日：2024-02-29

申请号：US18168504

申请日：2023-02-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Xiang You ,  Wei-De Ho ,  Hsin Yang Hung ,  Meng-Yu Lin ,  Hsiang-Hung Huang ,  Chun-Fu Cheng ,  Kuan-Kan Hu ,  Szu-Hua Chen ,  Ting-Yun Wu ,  Wei-Cheng Tzeng ,  Wei-Cheng Lin ,  Cheng-Yin Wang ,  Jui-Chien Huang ,  Szuya Liao

IPC: H01L29/06 ,  H01L21/8238 ,  H01L23/528 ,  H01L29/417 ,  H01L29/423 ,  H01L29/786

CPC classification number: H01L29/0673 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823878 ,  H01L23/5283 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/78696

Abstract: A device includes: a complementary transistor including: a first transistor having a first source/drain region and a second source/drain region; and a second transistor stacked on the first transistor, and having a third source/drain region and a fourth source/drain region, the third source/drain region overlapping the first source/drain region, the fourth source/drain region overlapping the second source/drain region. The device further includes: a first source/drain contact electrically coupled to the third source/drain region; a second source/drain contact electrically coupled to the second source/drain region; a gate isolation structure adjacent the first and second transistors; and an interconnect structure electrically coupled to the first source/drain contact and the second source/drain contact. The interconnect structure includes: a conductive layer in contact with the first source/drain contact and the second source/drain contact, the conductive layer being in the gate isolation structure; an opening in the conductive layer, the opening overlapping the fourth source/drain region, the second source/drain region or both; and a dielectric layer in the opening and on the conductive layer in the gate isolation structure.

公开(公告)号：US09786569B1

公开(公告)日：2017-10-10

申请号：US15334912

申请日：2016-10-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-De Ho ,  Shu-Hong Lin ,  Ya Hui Chang ,  Chih-Jung Chiang ,  Chang-Yi Tsai ,  Tsung-Lin Yang ,  Kuei-Shun Chen

IPC: H01L21/00 ,  H01L21/66 ,  H01L23/544 ,  H01L21/027

CPC classification number: H01L22/20 ,  G03F7/70633 ,  H01L22/12 ,  H01L23/544 ,  H01L2223/54426 ,  H01L2223/54453

Abstract: A method includes receiving a device having a first layer and a second layer over the first layer, the first layer having a first overlay mark. The method further includes forming a first resist pattern over the second layer, the first resist pattern having a second overlay mark. The method further includes performing a first overlay measurement using the second overlay mark in the first resist pattern and the first overlay mark; and performing one or more first manufacturing processes, thereby transferring the second overlay mark into the second layer and removing the first resist pattern. The method further includes performing one or more second manufacturing processes that include forming a third layer over the second layer. After the performing of the one or more second manufacturing processes, the method includes performing a second overlay measurement using the second overlay mark in the second layer and the first overlay mark.

公开(公告)号：US12119271B1

公开(公告)日：2024-10-15

申请号：US18545337

申请日：2023-12-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Bo Liao ,  Wei-De Ho ,  Cheng-Ting Chung ,  Szuya Liao

IPC: H01L21/8238 ,  H01L27/12 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L21/823871 ,  H01L27/124 ,  H01L27/1266 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66787 ,  H01L29/78696

Abstract: A method includes forming a first transistor and a second transistor over a semiconductor substrate, wherein the first transistor and the second transistor are vertically stacked. The method further includes exposing a backside of a first gate stack of the first transistor; forming a backside gate etch stop layer (ESL) on the backside of the first gate stack; patterning a contact opening through the backside gate ESL to expose the first gate stack; and forming a backside gate contact in the contact opening. The backside gate contact extends through the backside gate ESL to electrically connect to the first gate stack.

公开(公告)号：US20240282671A1

公开(公告)日：2024-08-22

申请号：US18327998

申请日：2023-06-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuan Yu Chen ,  Chun-Yen Lin ,  Hsin Yang Hung ,  Ching-Yu Huang ,  Wei-Cheng Lin ,  Jiann-Tyng Tzeng ,  Ting-Yun Wu ,  Wei-De Ho ,  Szuya Liao

IPC: H01L23/48 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/417 ,  H01L29/66

CPC classification number: H01L23/481 ,  H01L21/823814 ,  H01L21/823871 ,  H01L27/092 ,  H01L29/41733 ,  H01L29/66545

Abstract: A method includes forming a multi-layer stack comprising dummy layers and semiconductor layers located alternatingly, and forming a plurality of dummy gate stacks on sidewalls and a top surface of the multi-layer stack. Two of the plurality of dummy gate stacks are immediately neighboring each other, and have a space in between. A first source/drain region and a second source/drain region are formed in the multi-layer stack, with the second source/drain region overlapping the first source/drain region. The method further includes replacing the plurality of dummy gate stacks with a plurality of replacement gate stacks, replacing a first one of the plurality of replacement gate stacks with a first dielectric isolation region, forming a deep contact plug in the space, forming a front-side via over the deep contact plug, and forming a back-side via under the deep contact plug, wherein the front-side via is electrically connected to the back-side via through the deep contact plug.

公开(公告)号：US11804410B2

公开(公告)日：2023-10-31

申请号：US16810607

申请日：2020-03-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-De Ho ,  Han-Wei Wu ,  Pei-Sheng Tang ,  Meng-Jung Lee ,  Hua-Tai Lin ,  Szu-Ping Tung ,  Lan-Hsin Chiang

IPC: H01L21/66 ,  H01L21/67

CPC classification number: H01L22/12 ,  H01L21/67288

Abstract: A method for evaluation of thin film non-uniform stress using high order wafer warpage, the steps including measuring a net wafer warpage across a wafer area due to thin film deposition, fitting a two dimensional low-order polynomial to the wafer warpage measurements and subtracting the low-order polynomial from the net wafer warpage across the wafer area.