公开(公告)号：US20150031194A1

公开(公告)日：2015-01-29

申请号：US14511932

申请日：2014-10-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jen-Hang YANG ,  Chun-Fu CHEN ,  Pin-Dai SUE ,  Hui-Zhong ZHUANG

IPC: H01L21/28 ,  H01L21/768 ,  H01L23/60 ,  H01L21/283

CPC classification number: H01L21/28008 ,  H01L21/283 ,  H01L21/76895 ,  H01L23/60 ,  H01L27/0207 ,  H01L27/0629 ,  H01L27/0811 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An antenna cell for preventing plasma enhanced gate dielectric failures, is provided. The antenna cell design utilizes a polysilicon lead as a gate for a dummy transistor. The polysilicon lead may be one of a group of parallel, nested polysilicon lead. The dummy transistor includes the gate coupled to a substrate maintained at VSS, either directly through a metal lead or indirectly through a tie-low cell. The gate is disposed over a dielectric disposed over a continuous source/drain region in which the source and drain are tied together. A diode is formed with the semiconductor substrate within which it is formed. The source/drain region is coupled to another metal lead which may be an input pin and is coupled to active transistor gates, preventing plasma enhanced gate dielectric damage to the active transistors.

Abstract translation: 提供了一种用于防止等离子体增强的栅极介质故障的天线单元。 天线单元设计利用多晶硅引线作为虚拟晶体管的栅极。 多晶硅引线可以是一组并联的嵌套多晶硅引线之一。 虚拟晶体管包括连接到保持在VSS处的衬底的栅极，直接通过金属引线或间接地通过连接低电池连接。 栅极设置在设置在连续源极/漏极区域上的电介质上，其中源极和漏极连接在一起。 二极管与形成有半导体衬底的半导体衬底形成。 源极/漏极区域耦合到另一个金属引线，金属引线可以是输入引脚并且耦合到有源晶体管栅极，防止等离子体对有源晶体管的栅极介电损伤。