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    INTEGRATED CIRCUIT DEVICE
    1.
    发明申请
    INTEGRATED CIRCUIT DEVICE 有权

    公开(公告)号：US20240387504A1

    公开(公告)日：2024-11-21

    申请号：US18785842

    申请日：2024-07-26

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    Inventor： Chih-Liang CHEN ,  Shun Li CHEN ,  Li-Chun TIEN ,  Ting Yu CHEN ,  Hui-Zhong ZHUANG

    IPC: H01L27/02 ,  G06F30/392 ,  H01L27/092

    Abstract: An integrated circuit (IC) device includes first to fourth circuits configured to perform corresponding functions. The first to fourth circuits correspondingly include first to fourth active regions extending along a first direction, and further include a plurality of gate regions extending along a second direction transverse to the first direction. Adjacent gate regions among the plurality of gate regions are spaced from each other along the first direction by one gate region pitch. The first active region and the second active region correspondingly have a first source/drain region and a second source/drain region spaced from each other, along the first direction, by one gate region pitch. The first source/drain region is a drain region. The plurality of gate regions includes a dummy gate region between the first source/drain region and the second source/drain region. The third active region and the fourth active region share a common source region.

    INTEGRATED CIRCUIT
    3.
    发明申请
    INTEGRATED CIRCUIT 有权

    公开(公告)号：US20220302111A1

    公开(公告)日：2022-09-22

    申请号：US17834752

    申请日：2022-06-07

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    Inventor： Guo-Huei WU ,  Po-Chun WANG ,  Hui-Zhong ZHUANG ,  Chih-Liang CHEN ,  Li-Chun TIEN

    IPC: H01L27/092 ,  H01L29/06 ,  H01L23/538

    Abstract: A method is provided and includes operations below: forming a multilayer stack, wherein the multilayer stack includes multiple first semiconductor layers and multiple second semiconductor layers that are alternately stacked; forming a first source region and a first drain region on opposing sides of a first portion of the multilayer stack and forming a second source region and a second drain region on opposing sides of a second portion of the multilayer stack; removing the second semiconductor layers in the multilayer stack; forming a first gate region, corresponding to a first transistor, over the first portion of the multilayer stack; forming a first insulating layer above the first gate region; and forming a second gate region, corresponding to a second transistor, above the first insulating layer and over the second portion of the multilayer stack.

    MULTI-BIT STRUCTURE
    4.
    发明申请
    MULTI-BIT STRUCTURE 有权

    公开(公告)号：US20210407986A1

    公开(公告)日：2021-12-30

    申请号：US16915954

    申请日：2020-06-29

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    Inventor： Shao-Lun CHIEN ,  Po-Chun WANG ,  Hui-Zhong ZHUANG ,  Chih-Liang CHEN ,  Li-Chun TIEN

    IPC: H01L27/02 ,  H01L23/522 ,  G06F30/392

    Abstract: An integrated circuit disclosed here includes several cell rows extending in a first direction and a multi-bit cell having several bit cells included in the cell rows. The bit cells include M bit cells, and an output signal of a N-th bit cell of the M bit cells is an input signal of a (N+1)-th bit cell of the M bit cells, N and M being positive integers. A first bit cell of the bit cells and a M-th bit cell of the bit cells are arranged diagonally in different cell rows in the multi-bit cell, and the N-th bit cell and the (N+1)-th bit cell are arranged diagonally in different cell rows in the multi-bit cell.

    FOOTPRINT FOR MULTI-BIT FLIP FLOP
    5.
    发明申请
    FOOTPRINT FOR MULTI-BIT FLIP FLOP 有权

    公开(公告)号：US20210391850A1

    公开(公告)日：2021-12-16

    申请号：US16900765

    申请日：2020-06-12

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    Inventor： Po-Chun WANG ,  Hui-Zhong ZHUANG ,  Chih-Liang CHEN ,  Jerry Chang-Jui KAO ,  Tzu-Ying LIN

    IPC: H03K3/037 ,  H01L27/02 ,  G01R31/3187

    Abstract: An integrated circuit disclosed here includes a first plurality of cell rows, a second plurality of cell rows, first and second clock inverters, and a plurality of flip-flops. The second plurality of cell rows are arranged abutting the first plurality of cell rows. A first number of fins in the first plurality of cell rows is different from a second number of fins in the second plurality of cell rows. The first and second clock inverters are arranged in the second plurality of cell rows. The plurality of flip-flops are arranged in the first plurality of cell rows and the second plurality of cell rows. The plurality of flip-flops include a first plurality of flip-flops configured to operate in response to the first clock and second clock signals.

    INTEGRATED CIRCUIT
    6.
    发明申请
    INTEGRATED CIRCUIT 有权

    公开(公告)号：US20210366774A1

    公开(公告)日：2021-11-25

    申请号：US16882103

    申请日：2020-05-22

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    Inventor： Jerry Chang-Jui KAO ,  Hui-Zhong ZHUANG ,  Li-Chung HSU ,  Sung-Yen YEH ,  Yung-Chen CHIEN ,  Jung-Chan YANG ,  Tzu-Ying LIN

    IPC: H01L21/822 ,  H01L23/50 ,  H01L23/535 ,  H01L21/48

    Abstract: A semiconductor device includes several first cell rows extending in a first direction, each of the first cell rows having a first row height; several second cell rows extending in the first direction, each of the second cell rows having a second row height smaller than the first row height, wherein the first cell rows and the second cell rows are interlaced; a first cell arranged in a first row of the first cell rows; and at least one second cell arranged in at least one row of the second cell rows, wherein the at least one second cell abuts the first cell in a second direction different from the first direction, wherein the at least one second cell and at least one circuit component included in the first cell have the same operation configuration.

    MULTI-BIT STRUCTURE
    10.
    发明公开
    MULTI-BIT STRUCTURE 审中-公开

    公开(公告)号：US20240153942A1

    公开(公告)日：2024-05-09

    申请号：US18415211

    申请日：2024-01-17

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    Inventor： Shao-Lun CHIEN ,  Po-Chun WANG ,  Hui-Zhong ZHUANG ,  Chih-Liang CHEN ,  Li-Chun TIEN

    IPC: H01L27/02 ,  G06F30/392 ,  H01L23/522

    CPC classification number: H01L27/0207 ,  G06F30/392 ,  H01L23/5226

    Abstract: An integrated circuit is provided and includes a multi-bit cell having multiple bit cells disposed in multiple cell rows. The bit cells include M bit cells, M being positive integers. A first bit cell of the bit cells and a M-th bit cell of the bit cells are arranged diagonally in different cell rows in the multi-bit cell. The multi-bit cell includes first to fourth cell boundaries. The first and second boundaries extend in a first direction and the third and fourth boundaries extend in a second direction different from the first direction. The first bit cell and a second bit cell of the bit cells abut the third cell boundary, and the first bit cell and a (M/2+1)-th bit cell of the bit cells abut the first cell boundary.

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