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公开(公告)号：US12210200B2
公开(公告)日：2025-01-28
申请号：US18586919
申请日：2024-02-26
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Chung-Ming Weng , Chen-Hua Yu , Chung-Shi Liu , Hao-Yi Tsai , Cheng-Chieh Hsieh , Hung-Yi Kuo , Tsung-Yuan Yu , Hua-Kuei Lin , Che-Hsiang Hsu
Abstract: A package includes a photonic layer on a substrate, the photonic layer including a silicon waveguide coupled to a grating coupler; an interconnect structure over the photonic layer; an electronic die and a first dielectric layer over the interconnect structure, where the electronic die is connected to the interconnect structure; a first substrate bonded to the electronic die and the first dielectric layer; a socket attached to a top surface of the first substrate; and a fiber holder coupled to the first substrate through the socket, where the fiber holder includes a prism that re-orients an optical path of an optical signal.
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公开(公告)号：US11686908B2
公开(公告)日：2023-06-27
申请号：US17567497
申请日：2022-01-03
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Chung-Ming Weng , Chen-Hua Yu , Chung-Shi Liu , Hao-Yi Tsai , Cheng-Chieh Hsieh , Hung-Yi Kuo , Tsung-Yuan Yu , Hua-Kuei Lin , Che-Hsiang Hsu
CPC classification number: G02B6/43 , G02B6/4204 , G02B6/4214 , G02B6/4239 , G02B6/4253
Abstract: A package includes a photonic layer on a substrate, the photonic layer including a silicon waveguide coupled to a grating coupler; an interconnect structure over the photonic layer; an electronic die and a first dielectric layer over the interconnect structure, where the electronic die is connected to the interconnect structure; a first substrate bonded to the electronic die and the first dielectric layer; a socket attached to a top surface of the first substrate; and a fiber holder coupled to the first substrate through the socket, where the fiber holder includes a prism that re-orients an optical path of an optical signal.
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公开(公告)号：US20210223489A1
公开(公告)日：2021-07-22
申请号：US16930702
申请日：2020-07-16
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Chung-Ming Weng , Chen-Hua Yu , Chung-Shi Liu , Hao-Yi Tsai , Cheng-Chieh Hsieh , Hung-Yi Kuo , Chih-Hsuan Tai , Hua-Kuei Lin , Tsung-Yuan Yu , Min-Hsiang Hsu
Abstract: Photonic devices and methods of manufacture are provided. In embodiments a fill material and/or a secondary waveguide are utilized in order to protect other internal structures such as grating couplers from the rigors of subsequent processing steps. Through the use of these structures at the appropriate times during the manufacturing process, damage and debris that would otherwise interfere with the manufacturing process of the device or operation of the device can be avoided.
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公开(公告)号：US20250157989A1
公开(公告)日：2025-05-15
申请号：US18591758
申请日：2024-02-29
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Chung-Ming Weng , An-Jhih Su , Tzuan-Horng Liu
IPC: H01L25/065 , H01L23/00 , H01L23/48 , H01L23/58 , H01L25/00
Abstract: A method includes forming a die, which further includes forming a first through-via and a second through-via extending from a front side of a semiconductor substrate into the semiconductor substrate. The first through-via and the second through-via are connected to a first integrated circuit device and a second integrated circuit device, respectively, in the die. A backside grinding process is performed to reveal the first through-via and the second through-via. A backside redistribution line is formed to physically join to both of the first through-via and the second through-via.
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5.发明公开公开(公告)号：US20230384538A1
公开(公告)日：2023-11-30
申请号：US18232317
申请日：2023-08-09
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Yu-Hao CHEN , Hui-Yu Lee , Chung-Ming Weng , Jui-Feng Kuan , Chien-Te Wu
CPC classification number: G02B6/4214 , G02B6/4204 , G02B6/4201 , G02B6/1221
Abstract: Disclosed are apparatus and methods for a silicon photonic (SiPh) structure comprising the integration of an electrical integrated circuit (EIC); a photonic integrated circuit (PIC) disposed on top of the EIC; two or more polymer waveguides (PWGs) disposed on top of the PIC and formed by layers of cladding polymer and core polymer; and an integration fan-out redistribution (InFO RDL) layer disposed on top of the two or more PWGs. The operation of PWGs is based on the refractive indexes of the cladding and core polymers. Inter-layer optical signals coupling is provided by edge-coupling, reflective prisms and grating coupling. A wafer-level system implements a SiPh structure die and provides inter-die signal optical interconnections among the PWGs.
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Patent Agency Ranking
6.发明授权公开(公告)号：US11740415B2
公开(公告)日：2023-08-29
申请号：US17320596
申请日：2021-05-14
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Yu-Hao Chen , Hui-Yu Lee , Chung-Ming Weng , Jui-Feng Kuan , Chien-Te Wu
CPC classification number: G02B6/4214 , G02B6/1221 , G02B6/4201 , G02B6/4204
Abstract: Disclosed are apparatus and methods for a silicon photonic (SiPh) structure comprising the integration of an electrical integrated circuit (EIC); a photonic integrated circuit (PIC) disposed on top of the EIC; two or more polymer waveguides (PWGs) disposed on top of the PIC and formed by layers of cladding polymer and core polymer; and an integration fan-out redistribution (InFO RDL) layer disposed on top of the two or more PWGs. The operation of PWGs is based on the refractive indexes of the cladding and core polymers. Inter-layer optical signals coupling is provided by edge-coupling, reflective prisms and grating coupling. A wafer-level system implements a SiPh structure die and provides inter-die signal optical interconnections among the PWGs.
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公开(公告)号：US11614592B2
公开(公告)日：2023-03-28
申请号：US16930702
申请日：2020-07-16
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Chung-Ming Weng , Chen-Hua Yu , Chung-Shi Liu , Hao-Yi Tsai , Cheng-Chieh Hsieh , Hung-Yi Kuo , Chih-Hsuan Tai , Hua-Kuei Lin , Tsung-Yuan Yu , Min-Hsiang Hsu
Abstract: Photonic devices and methods of manufacture are provided. In embodiments a fill material and/or a secondary waveguide are utilized in order to protect other internal structures such as grating couplers from the rigors of subsequent processing steps. Through the use of these structures at the appropriate times during the manufacturing process, damage and debris that would otherwise interfere with the manufacturing process of the device or operation of the device can be avoided.
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公开(公告)号：US12222545B2
公开(公告)日：2025-02-11
申请号：US18302046
申请日：2023-04-18
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Chih-Hsuan Tai , Chung-Ming Weng , Hung-Yi Kuo , Cheng-Chieh Hsieh , Hao-Yi Tsai , Chung-Shi Liu , Chen-Hua Yu
IPC: G02B6/13 , G02B6/12 , G02B6/30 , G02B6/42 , G02B6/43 , H01L21/56 , H01L21/683 , H01L23/00 , H01L23/492 , H01L23/498 , H01L25/16 , H01L23/31
Abstract: An integrated circuit package and a method of forming the same are provided. The integrated circuit package includes a photonic integrated circuit die. The photonic integrated circuit die includes an optical coupler. The integrated circuit package further includes an encapsulant encapsulating the photonic integrated circuit die, a first redistribution structure over the photonic integrated circuit die and the encapsulant, and an opening extending through the first redistribution structure and exposing the optical coupler.
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公开(公告)号：US20230280558A1
公开(公告)日：2023-09-07
申请号：US18312767
申请日：2023-05-05
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Chung-Ming Weng , Chen-Hua Yu , Chung-Shi Liu , Hao-Yi Tsai , Cheng-Chieh Hsieh , Hung-Yi Kuo , Tsung-Yuan Yu , Hua-Kuei Lin , Che-Hsiang Hsu
CPC classification number: G02B6/43 , G02B6/4204 , G02B6/4214 , G02B6/4253 , G02B6/4239
Abstract: A package includes a photonic layer on a substrate, the photonic layer including a silicon waveguide coupled to a grating coupler; an interconnect structure over the photonic layer; an electronic die and a first dielectric layer over the interconnect structure, where the electronic die is connected to the interconnect structure; a first substrate bonded to the electronic die and the first dielectric layer; a socket attached to a top surface of the first substrate; and a fiber holder coupled to the first substrate through the socket, where the fiber holder includes a prism that re-orients an optical path of an optical signal.
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公开(公告)号：US20230266528A1
公开(公告)日：2023-08-24
申请号：US18302046
申请日：2023-04-18
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Chih-Hsuan Tai , Chung-Ming Weng , Hung-Yi Kuo , Cheng-Chieh Hsieh , Hao-Yi Tsai , Chung-Shi Liu , Chen-Hua Yu
IPC: G02B6/12 , G02B6/42 , H01L23/498 , G02B6/13 , G02B6/43
CPC classification number: G02B6/12004 , G02B6/13 , G02B6/43 , G02B6/4249 , H01L23/49827 , H01L23/49838 , G02B2006/12147
Abstract: An integrated circuit package and a method of forming the same are provided. The integrated circuit package includes a photonic integrated circuit die. The photonic integrated circuit die includes an optical coupler. The integrated circuit package further includes an encapsulant encapsulating the photonic integrated circuit die, a first redistribution structure over the photonic integrated circuit die and the encapsulant, and an opening extending through the first redistribution structure and exposing the optical coupler.
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