公开(公告)号：US20230384538A1

公开(公告)日：2023-11-30

申请号：US18232317

申请日：2023-08-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Hao CHEN ,  Hui-Yu Lee ,  Chung-Ming Weng ,  Jui-Feng Kuan ,  Chien-Te Wu

IPC: G02B6/42 ,  G02B6/122

CPC classification number: G02B6/4214 ,  G02B6/4204 ,  G02B6/4201 ,  G02B6/1221

Abstract: Disclosed are apparatus and methods for a silicon photonic (SiPh) structure comprising the integration of an electrical integrated circuit (EIC); a photonic integrated circuit (PIC) disposed on top of the EIC; two or more polymer waveguides (PWGs) disposed on top of the PIC and formed by layers of cladding polymer and core polymer; and an integration fan-out redistribution (InFO RDL) layer disposed on top of the two or more PWGs. The operation of PWGs is based on the refractive indexes of the cladding and core polymers. Inter-layer optical signals coupling is provided by edge-coupling, reflective prisms and grating coupling. A wafer-level system implements a SiPh structure die and provides inter-die signal optical interconnections among the PWGs.

公开(公告)号：US11740415B2

公开(公告)日：2023-08-29

申请号：US17320596

申请日：2021-05-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Hao Chen ,  Hui-Yu Lee ,  Chung-Ming Weng ,  Jui-Feng Kuan ,  Chien-Te Wu

IPC: G02B6/42 ,  G02B6/122 ,  H01L25/16

CPC classification number: G02B6/4214 ,  G02B6/1221 ,  G02B6/4201 ,  G02B6/4204

Abstract: Disclosed are apparatus and methods for a silicon photonic (SiPh) structure comprising the integration of an electrical integrated circuit (EIC); a photonic integrated circuit (PIC) disposed on top of the EIC; two or more polymer waveguides (PWGs) disposed on top of the PIC and formed by layers of cladding polymer and core polymer; and an integration fan-out redistribution (InFO RDL) layer disposed on top of the two or more PWGs. The operation of PWGs is based on the refractive indexes of the cladding and core polymers. Inter-layer optical signals coupling is provided by edge-coupling, reflective prisms and grating coupling. A wafer-level system implements a SiPh structure die and provides inter-die signal optical interconnections among the PWGs.

公开(公告)号：US12181722B2

公开(公告)日：2024-12-31

申请号：US18232317

申请日：2023-08-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Hao Chen ,  Hui-Yu Lee ,  Chung-Ming Weng ,  Jui-Feng Kuan ,  Chien-Te Wu

IPC: G02B6/42 ,  G02B6/122 ,  H01L21/50 ,  H01L21/683 ,  H01L23/00 ,  H01L25/16

Abstract: Disclosed are apparatus and methods for a silicon photonic (SiPh) structure comprising the integration of an electrical integrated circuit (EIC); a photonic integrated circuit (PIC) disposed on top of the EIC; two or more polymer waveguides (PWGs) disposed on top of the PIC and formed by layers of cladding polymer and core polymer; and an integration fan-out redistribution (InFO RDL) layer disposed on top of the two or more PWGs. The operation of PWGs is based on the refractive indexes of the cladding and core polymers. Inter-layer optical signals coupling is provided by edge-coupling, reflective prisms and grating coupling. A wafer-level system implements a SiPh structure die and provides inter-die signal optical interconnections among the PWGs.

公开(公告)号：US11670610B2

公开(公告)日：2023-06-06

申请号：US16801160

申请日：2020-02-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Feng-Wei Kuo ,  Hui-Yu Lee

IPC: G06F30/30 ,  H01L23/00 ,  G01R31/317 ,  G06F30/398 ,  G06F30/31

CPC classification number: H01L24/11 ,  G01R31/31704 ,  G06F30/31 ,  G06F30/398 ,  H01L2224/051 ,  H01L2224/11011 ,  H01L2924/14

Abstract: A method and a system for verifying an integrated circuit stack having at least one silicon photonic device is introduced. A dummy layer and a dummy layer text are added to a terminal of at least one silicon photonic device of the integrated circuit. The method may perform a layout versus schematic check of the integrated circuit including the dummy layer and the dummy layer text.

公开(公告)号：US11532613B2

公开(公告)日：2022-12-20

申请号：US17163960

申请日：2021-02-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hui-Yu Lee ,  Chi-Wen Chang ,  Jui-Feng Kuan ,  Yi-Kan Cheng

IPC: H01L23/34 ,  H01L23/38 ,  H01L27/06 ,  H01L23/00 ,  H01L25/065 ,  H01L35/26 ,  H01L35/18 ,  H01L23/48

Abstract: A structure and method for cooling a three-dimensional integrated circuit (3DIC) are provided. A cooling element is configured for thermal connection to the 3DIC. The cooling element includes a plurality of individually controllable cooling modules disposed at a first plurality of locations relative to the 3DIC. Each of the cooling modules includes a cold pole and a heat sink. The cold pole is configured to absorb heat from the 3DIC. The heat sink is configured to dissipate the heat absorbed by the cold pole and is coupled to the cold pole via an N-type semiconductor element and via a P-type semiconductor element. A temperature sensing element includes a plurality of thermal monitoring elements disposed at a second plurality of locations relative to the 3DIC for measuring temperatures at the second plurality of locations. The measured temperatures control the plurality of cooling modules.

公开(公告)号：US20210159225A1

公开(公告)日：2021-05-27

申请号：US17163960

申请日：2021-02-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hui-Yu Lee ,  Chi-Wen Chang ,  Jui-Feng Kuan ,  Yi-Kan Cheng

IPC: H01L27/06 ,  H01L23/34 ,  H01L23/00 ,  H01L23/38 ,  H01L25/065 ,  H01L35/26 ,  H01L35/18

Abstract: A structure and method for cooling a three-dimensional integrated circuit (3DIC) are provided. A cooling element is configured for thermal connection to the 3DIC. The cooling element includes a plurality of individually controllable cooling modules disposed at a first plurality of locations relative to the 3DIC. Each of the cooling modules includes a cold pole and a heat sink. The cold pole is configured to absorb heat from the 3DIC. The heat sink is configured to dissipate the heat absorbed by the cold pole and is coupled to the cold pole via an N-type semiconductor element and via a P-type semiconductor element. A temperature sensing element includes a plurality of thermal monitoring elements disposed at a second plurality of locations relative to the 3DIC for measuring temperatures at the second plurality of locations. The measured temperatures control the plurality of cooling modules.

公开(公告)号：US20210057365A1

公开(公告)日：2021-02-25

申请号：US16801160

申请日：2020-02-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Feng-Wei Kuo ,  Hui-Yu Lee

IPC: H01L23/00

Abstract: A method and a system for verifying an integrated circuit stack having at least one silicon photonic device is introduced. A dummy layer and a dummy layer text are added to a terminal of at least one silicon photonic device of the integrated circuit. The method may perform a layout versus schematic check of the integrated circuit including the dummy layer and the dummy layer text.

公开(公告)号：US10162244B1

公开(公告)日：2018-12-25

申请号：US15663489

申请日：2017-07-28

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Hui-Yu Lee ,  Jui-Feng Kuan

IPC: G02F1/00 ,  G02F1/01 ,  H03M1/06 ,  H03M1/12 ,  G02F1/225

Abstract: A device is disclosed that includes a comparator and a configurable heater. The comparator is configured to compare a transmission phase of a light transmitted in a photonic component with a reference phase to generate a phase difference. The configurable heater is disposed with respect to the photonic component and includes a plurality of heater segments, wherein a number of the heater segments in operation is trimmable based on the phase difference.