公开(公告)号：US10290535B1

公开(公告)日：2019-05-14

申请号：US15928896

申请日：2018-03-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Te Ho ,  Shih-Yu Chang ,  Da-Wei Lin ,  Chien-Chih Chiu ,  Ming-Chung Liang

IPC: H01L21/768 ,  H01L21/321 ,  H01L21/311

Abstract: Examples of fabricating an integrated circuit device are disclosed herein. In an embodiment, an integrated circuit workpiece is received that includes a conductive interconnect feature. A first Inter-Level Dielectric (ILD) layer is formed on the conductive interconnect feature, and a second ILD layer is formed on the first ILD layer. A hard mask is formed on the second ILD layer. A via recess is etched extending through the first ILD layer, the second ILD layer and the hard mask to expose the conductive interconnect feature. The etching includes providing a passivation agent that reacts with a material of the hard mask to reduce etchant sensitivity.