公开(公告)号：US20240387227A1

公开(公告)日：2024-11-21

申请号：US18787978

申请日：2024-07-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Yu Chang ,  Chien-Han Chen ,  Chien-Chih Chiu ,  Chi-Che Tseng

IPC: H01L21/683 ,  H01L21/3065 ,  H01L21/67 ,  H01L21/687 ,  H01L21/8238

Abstract: Semiconductor devices, methods of manufacturing the semiconductor device and tools are disclosed herein. Some methods include providing an electrostatic chuck and placing an edge ring adjacent to the electrostatic chuck. The electrostatic chuck includes a first electrode to generate a sheath at a first distance over the electrostatic chuck. The edge ring includes a coil and a second electrode to generate an electric field control to maintain a portion of the sheath over the edge ring in a coplanar orientation with the portion of the sheath over the electrostatic chuck.

公开(公告)号：US20230155001A1

公开(公告)日：2023-05-18

申请号：US17651347

申请日：2022-02-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chien-Han Chen ,  Shih-Yu Chang ,  Chien-Chih Chiu ,  Huang-Ming Chen ,  Jyu-Horng Shieh

IPC: H01L29/66 ,  H01L21/768 ,  H01L23/522 ,  H01L29/417 ,  H01L21/8234

CPC classification number: H01L29/66545 ,  H01L21/76897 ,  H01L21/76831 ,  H01L21/76877 ,  H01L23/5226 ,  H01L21/76807 ,  H01L29/41791 ,  H01L21/823475

Abstract: A method includes forming a transistor comprising a source/drain region and a gate electrode, forming a source/drain contact plug over and electrically connecting to the source/drain region, forming a first inter-layer dielectric over the source/drain contact plug, forming an etch stop layer over the first inter-layer dielectric, etching the etch stop layer to form a first via opening, forming a second inter-layer dielectric over the first inter-layer dielectric, performing an etching process, so that the second inter-layer dielectric is etched to form a trench, and the first via opening in the etch stop layer is extended into the first inter-layer dielectric to reveal the source/drain contact plug, and filling the trench and the first via opening in common processes to form a metal line and a via, respectively.

公开(公告)号：US10290535B1

公开(公告)日：2019-05-14

申请号：US15928896

申请日：2018-03-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Te Ho ,  Shih-Yu Chang ,  Da-Wei Lin ,  Chien-Chih Chiu ,  Ming-Chung Liang

IPC: H01L21/768 ,  H01L21/321 ,  H01L21/311

Abstract: Examples of fabricating an integrated circuit device are disclosed herein. In an embodiment, an integrated circuit workpiece is received that includes a conductive interconnect feature. A first Inter-Level Dielectric (ILD) layer is formed on the conductive interconnect feature, and a second ILD layer is formed on the first ILD layer. A hard mask is formed on the second ILD layer. A via recess is etched extending through the first ILD layer, the second ILD layer and the hard mask to expose the conductive interconnect feature. The etching includes providing a passivation agent that reacts with a material of the hard mask to reduce etchant sensitivity.

公开(公告)号：US20220367226A1

公开(公告)日：2022-11-17

申请号：US17520301

申请日：2021-11-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Yu Chang ,  Chien-Han Chen ,  Chien-Chih Chiu ,  Chi-Che Tseng

IPC: H01L21/683 ,  H01L21/687 ,  H01L21/67

Abstract: Semiconductor devices, methods of manufacturing the semiconductor device and tools are disclosed herein. Some methods include providing an electrostatic chuck and placing an edge ring adjacent to the electrostatic chuck. The electrostatic chuck includes a first electrode to generate a sheath at a first distance over the electrostatic chuck. The edge ring includes a coil and a second electrode to generate an electric field control to maintain a portion of the sheath over the edge ring in a coplanar orientation with the portion of the sheath over the electrostatic chuck.