公开(公告)号：US12051646B2

公开(公告)日：2024-07-30

申请号：US17402897

申请日：2021-08-16

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Hsiang-Lun Kao ,  Hsiang-Wei Liu ,  Tai-I Yang ,  Jian-Hua Chen ,  Yu-Chieh Liao ,  Yung-Chih Wang ,  Tien-Lu Lin

IPC分类号： H01L23/528 ,  H01L21/263 ,  H01L21/311 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532

CPC分类号： H01L23/5283 ,  H01L21/2633 ,  H01L21/31111 ,  H01L21/7682 ,  H01L21/76879 ,  H01L21/76885 ,  H01L23/5222 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53295 ,  H01L21/76834 ,  H01L2924/0002 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method comprises forming a first conductive line and a second conductive line in a first dielectric layer over a substrate, each having a planar top surface, applying an etch-back process to the first dielectric layer until a dielectric portion between the first conductive line and the second conductive line has been removed, and the first conductive line and the second conductive line have respective cross sectional shapes including a rounded surface and two rounded corners and depositing a second dielectric layer over the substrate, while leaving a first air gap between the first conductive line and the second conductive line.

公开(公告)号：US20210375760A1

公开(公告)日：2021-12-02

申请号：US17402897

申请日：2021-08-16

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Hsiang-Lun Kao ,  Hsiang-Wei Liu ,  Tai-I Yang ,  Jian-Hua Chen ,  Yu-Chieh Liao ,  Yung-Chih Wang ,  Tien-Lu Lin

IPC分类号： H01L23/528 ,  H01L23/522 ,  H01L21/311 ,  H01L21/768 ,  H01L21/263 ,  H01L23/532

摘要： A method comprises forming a first conductive line and a second conductive line in a first dielectric layer over a substrate, each having a planar top surface, applying an etch-back process to the first dielectric layer until a dielectric portion between the first conductive line and the second conductive line has been removed, and the first conductive line and the second conductive line have respective cross sectional shapes including a rounded surface and two rounded corners and depositing a second dielectric layer over the substrate, while leaving a first air gap between the first conductive line and the second conductive line.