公开(公告)号：US10964559B2

公开(公告)日：2021-03-30

申请号：US14320181

申请日：2014-06-30

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Tai-I Yang ,  Chih-Shen Yang ,  Tien-Lu Lin

IPC分类号： H01L21/67 ,  H01L21/311

摘要： A wafer etching apparatus and a method for controlling an etch bath of a wafer is provided. The wafer etching apparatus includes an etching tank comprising an etch bath, an etch bath recycle system connected to the etching tank, a real time monitor (RTM) system connected to the etching tank, and a control system coupled with the RTM system and the etch bath recycle system. The wafer etching apparatus and the method for controlling an etch bath of the wafer both control the silicate concentration in the etch bath to stable an etching selectivity with respect to silicon oxide and silicon nitride.

公开(公告)号：US10930551B2

公开(公告)日：2021-02-23

申请号：US16455840

申请日：2019-06-28

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Hsin-Yen Huang ,  Shao-Kuan Lee ,  Cheng-Chin Lee ,  Hsiang-Wei Liu ,  Tai-I Yang ,  Chia-Tien Wu ,  Hai-Ching Chen ,  Shau-Lin Shue

IPC分类号： H01L23/52 ,  H01L21/768 ,  H01L29/45 ,  H01L23/528

摘要： Integrated circuit devices and methods of forming the same are provided. A method according to the present disclosure includes providing a workpiece including a first metal feature in a dielectric layer and a capping layer over the first metal feature, selectively depositing a blocking layer over the capping layer, depositing an etch stop layer (ESL) over the workpiece, removing the blocking layer, and depositing a second metal feature over the workpiece such that the first metal feature is electrically coupled to the second metal feature. The blocking layer prevents the ESL from being deposited over the capping layer.

公开(公告)号：US20190244897A1

公开(公告)日：2019-08-08

申请号：US16384027

申请日：2019-04-15

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Hsiang-Wei Liu ,  Tai-I Yang ,  Cheng-Chi Chuang ,  Tien-Lu Lin

IPC分类号： H01L23/528 ,  H01L23/522 ,  H01L23/532 ,  H01L21/768

摘要： The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a dielectric structure over a substrate, and a first interconnect structure arranged within the dielectric structure. A lower interconnect structure is arranged within the dielectric structure. The first interconnect structure and the lower interconnect structure comprise one or more different conductive materials. The first interconnect structure continuously extends from directly over a topmost surface of the lower interconnect structure facing away from the substrate to along opposing outer sidewalls of the lower interconnect structure.

公开(公告)号：US10026647B2

公开(公告)日：2018-07-17

申请号：US15498259

申请日：2017-04-26

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Wei-Chen Chu ,  Tai-I Yang ,  Cheng-Chi Chuang ,  Chia-Tien Wu

IPC分类号： H01L21/768 ,  H01L21/311 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532

CPC分类号： H01L21/76816 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/76811 ,  H01L21/76813

摘要： The present disclosure describes methods which employ a patterning photolithography/etch operations to form self-aligned interconnects with multi-metal gap fill. For example, the method includes a first pattern structure and a second pattern structure formed over a dielectric layer. Each of the first and second pattern structures includes a pair of spacers, and a center portion between the pair of spacers. A first opening, self-aligned to a space between the first and second pattern structures, is formed in the dielectric layer. A first conductive material is deposited in the first opening. The center portion of the second pattern structure is removed to form a void above the dielectric layer and between the pair of spacers of the second pattern structure. A second opening, self-aligned to the void, is formed in the dielectric layer; and a second conductive material is deposited in the second opening.

公开(公告)号：US10002826B2

公开(公告)日：2018-06-19

申请号：US14524228

申请日：2014-10-27

申请人： Taiwan Semiconductor Manufacturing Co., Ltd

发明人： Tai-I Yang ,  Yu-Chieh Liao ,  Tien-Lu Lin ,  Tien-I Bao

IPC分类号： H01L29/76 ,  H01L23/522 ,  H01L23/485 ,  H01L29/417 ,  H01L29/78 ,  H01L21/768 ,  H01L23/532 ,  H01L29/66

CPC分类号： H01L23/5226 ,  H01L21/76805 ,  H01L21/76816 ,  H01L21/76831 ,  H01L21/76879 ,  H01L21/76885 ,  H01L21/76897 ,  H01L23/485 ,  H01L23/53228 ,  H01L23/53257 ,  H01L29/41758 ,  H01L29/665 ,  H01L29/7833 ,  H01L29/7848 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate. The semiconductor device structure includes a first dielectric layer over the semiconductor substrate. The semiconductor device structure includes a first conductive line embedded in the first dielectric layer. The semiconductor device structure includes a second dielectric layer over the first dielectric layer and the first conductive line. The semiconductor device structure includes a second conductive line over the second dielectric layer. The second dielectric layer is between the first conductive line and the second conductive line. The semiconductor device structure includes conductive pillars passing through the second dielectric layer to electrically connect the first conductive line to the second conductive line. The conductive pillars are spaced apart from each other.

公开(公告)号：US09875967B2

公开(公告)日：2018-01-23

申请号：US15464759

申请日：2017-03-21

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Tai-I Yang ,  Cheng-Chi Chuang ,  Yung-Chih Wang ,  Tien-Lu Lin

IPC分类号： H01L23/528 ,  H01L23/532 ,  H01L21/768

CPC分类号： H01L23/5283 ,  H01L21/76802 ,  H01L21/76804 ,  H01L21/76807 ,  H01L21/7682 ,  H01L21/76831 ,  H01L21/76834 ,  H01L21/76843 ,  H01L21/76877 ,  H01L21/76879 ,  H01L23/5221 ,  H01L23/5226 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2221/1063 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present disclosure relates to an interconnect structure. In some embodiments, the interconnect structure has a first conductive body arranged within a first dielectric layer over a substrate. A first air-gap separates sidewalls of the first conductive body from the first dielectric layer. A barrier layer is arranged on sidewalls of the first conductive body at a location between the first conductive body and the first air-gap. The first air-gap is defined by a sidewall of the barrier layer and an opposing sidewall of the first dielectric layer.

公开(公告)号：US20170194259A1

公开(公告)日：2017-07-06

申请号：US15464759

申请日：2017-03-21

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Tai-I Yang ,  Cheng-Chi Chuang ,  Yung-Chih Wang ,  Tien-Lu Lin

IPC分类号： H01L23/528 ,  H01L23/532 ,  H01L21/768

CPC分类号： H01L23/5283 ,  H01L21/76802 ,  H01L21/76804 ,  H01L21/76807 ,  H01L21/7682 ,  H01L21/76831 ,  H01L21/76834 ,  H01L21/76843 ,  H01L21/76877 ,  H01L21/76879 ,  H01L23/5221 ,  H01L23/5226 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2221/1063 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present disclosure relates to an interconnect structure. In some embodiments, the interconnect structure has a first conductive body arranged within a first dielectric layer over a substrate. A first air-gap separates sidewalls of the first conductive body from the first dielectric layer. A barrier layer is arranged on sidewalls of the first conductive body at a location between the first conductive body and the first air-gap. The first air-gap is defined by a sidewall of the barrier layer and an opposing sidewall of the first dielectric layer.

公开(公告)号：US09633897B2

公开(公告)日：2017-04-25

申请号：US15170059

申请日：2016-06-01

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Tai-I Yang ,  Cheng-Chi Chuang ,  Yung-Chih Wang ,  Tien-Lu Lin

IPC分类号： H01L21/768 ,  H01L23/532 ,  H01L23/522

CPC分类号： H01L23/5283 ,  H01L21/76802 ,  H01L21/76804 ,  H01L21/76807 ,  H01L21/7682 ,  H01L21/76831 ,  H01L21/76834 ,  H01L21/76843 ,  H01L21/76877 ,  H01L21/76879 ,  H01L23/5221 ,  H01L23/5226 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2221/1063 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present disclosure relates to a method of forming an interconnect structure. In some embodiments, the method is performed by forming a trench within a first dielectric layer and forming sacrificial spacers along sidewalls of the trench. The trench is filled with a conductive material, and the sacrificial spacers are removed after the trench has been filled with the conductive material. A second dielectric layer is formed over the first dielectric layer to leave an air-gap in a region from which the sacrificial spacers were removed.

公开(公告)号：US09390965B2

公开(公告)日：2016-07-12

申请号：US14135785

申请日：2013-12-20

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Tai-I Yang ,  Cheng-Chi Chuang ,  Yung-Chih Wang ,  Tien-Lu Lin

IPC分类号： H01L21/768 ,  H01L23/532 ,  H01L23/522

CPC分类号： H01L23/5283 ,  H01L21/76802 ,  H01L21/76804 ,  H01L21/76807 ,  H01L21/7682 ,  H01L21/76831 ,  H01L21/76834 ,  H01L21/76843 ,  H01L21/76877 ,  H01L21/76879 ,  H01L23/5221 ,  H01L23/5226 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2221/1063 ,  H01L2924/0002 ,  H01L2924/00

摘要： An interconnect structure includes a first low-k dielectric layer formed over a substrate. A first metal line is disposed in the first low-k dielectric layer. The first metal line includes a first conductive body with a first width and an up landing pad with a second width. The first width is smaller than the second width. The interconnect structure further includes a first air-gap adjacent to sidewalls of the first conductive body. The interconnect structure also includes a second low-k dielectric layer formed over the first low-k dielectric layer and a first via in the second low-k dielectric layer and disposed on the up landing pad.

摘要翻译： 互连结构包括在衬底上形成的第一低k电介质层。 第一金属线设置在第一低k电介质层中。 第一金属线包括具有第一宽度的第一导电体和具有第二宽度的向上着陆垫。 第一宽度小于第二宽度。 互连结构还包括与第一导电体的侧壁相邻的第一气隙。 互连结构还包括形成在第一低k电介质层上的第二低k电介质层和第二低k电介质层中的第一通孔，并设置在上焊垫上。

公开(公告)号：US20150179499A1

公开(公告)日：2015-06-25

申请号：US14135785

申请日：2013-12-20

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Tai-I Yang ,  Cheng-Chi Chuang ,  Yung-Chih Wang ,  Tien-Lu Lin

IPC分类号： H01L21/768 ,  H01L23/532 ,  H01L23/528

CPC分类号： H01L23/5283 ,  H01L21/76802 ,  H01L21/76804 ,  H01L21/76807 ,  H01L21/7682 ,  H01L21/76831 ,  H01L21/76834 ,  H01L21/76843 ,  H01L21/76877 ,  H01L21/76879 ,  H01L23/5221 ,  H01L23/5226 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2221/1063 ,  H01L2924/0002 ,  H01L2924/00

摘要： An interconnect structure includes a first low-k dielectric layer formed over a substrate. A first metal line is disposed in the first low-k dielectric layer. The first metal line includes a first conductive body with a first width and an up landing pad with a second width. The first width is smaller than the second width. The interconnect structure further includes a first air-gap adjacent to sidewalls of the first conductive body. The interconnect structure also includes a second low-k dielectric layer formed over the first low-k dielectric layer and a first via in the second low-k dielectric layer and disposed on the up landing pad.

摘要翻译： 互连结构包括在衬底上形成的第一低k电介质层。 第一金属线设置在第一低k电介质层中。 第一金属线包括具有第一宽度的第一导电体和具有第二宽度的向上着陆垫。 第一宽度小于第二宽度。 互连结构还包括与第一导电体的侧壁相邻的第一气隙。 互连结构还包括形成在第一低k电介质层上的第二低k电介质层和第二低k电介质层中的第一通孔，并设置在上焊垫上。