公开(公告)号：US20200043939A1

公开(公告)日：2020-02-06

申请号：US16527044

申请日：2019-07-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Cheng Wu ,  Hung-Pin Ko

IPC: H01L27/11526 ,  G11C16/04 ,  G11C16/08

Abstract: Provided are a semiconductor device and a method of manufacturing the same. The semiconductor device includes a substrate, a first FET, and a second FET formed over the substrate. The substrate has a first surface and a second surface, and the first surface and the second surface form a step. The first FET comprises a first gate dielectric layer over the first surface of the substrate. The second FET comprises a second gate dielectric layer thinner than the first gate dielectric layer over the second surface of the substrate.

公开(公告)号：US11158644B2

公开(公告)日：2021-10-26

申请号：US16527044

申请日：2019-07-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Cheng Wu ,  Hung-Pin Ko

IPC: H01L27/11526 ,  G11C16/08 ,  G11C16/04

Abstract: Provided are a semiconductor device and a method of manufacturing the same. The semiconductor device includes a substrate, a first FET, and a second FET formed over the substrate. The substrate has a first surface and a second surface, and the first surface and the second surface form a step. The first FET comprises a first gate dielectric layer over the first surface of the substrate. The second FET comprises a second gate dielectric layer thinner than the first gate dielectric layer over the second surface of the substrate.

公开(公告)号：US20200251566A1

公开(公告)日：2020-08-06

申请号：US16580296

申请日：2019-09-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei Cheng Wu ,  Alexander Kalnitsky ,  Shih-Hao Lo ,  Hung-Pin Ko

IPC: H01L29/423 ,  H01L29/66

Abstract: Various embodiments of the present disclosure are directed towards a semiconductor device including a gate structure. The semiconductor device further includes a pair of spacer segments on a semiconductor substrate. A high-κ gate dielectric structure overlies the semiconductor substrate. The high-κ gate dielectric structure is laterally between and borders the spacer segments. The gate structure overlies the high-k gate dielectric structure and has a top surface about even with a top surface of the spacer segments. The gate structure includes a metal structure and a gate body layer. The gate body layer has a top surface that is vertically offset from a top surface of the metal structure and further has a lower portion cupped by the metal structure.

公开(公告)号：US11335786B2

公开(公告)日：2022-05-17

申请号：US16580296

申请日：2019-09-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei Cheng Wu ,  Alexander Kalnitsky ,  Shih-Hao Lo ,  Hung-Pin Ko

IPC: H01L29/49 ,  H01L29/423 ,  H01L29/66

Abstract: Various embodiments of the present disclosure are directed towards a semiconductor device including a gate structure. The semiconductor device further includes a pair of spacer segments on a semiconductor substrate. A high-κ gate dielectric structure overlies the semiconductor substrate. The high-κ gate dielectric structure is laterally between and borders the spacer segments. The gate structure overlies the high-k gate dielectric structure and has a top surface about even with a top surface of the spacer segments. The gate structure includes a metal structure and a gate body layer. The gate body layer has a top surface that is vertically offset from a top surface of the metal structure and further has a lower portion cupped by the metal structure.