公开(公告)号：US11257816B2

公开(公告)日：2022-02-22

申请号：US16794044

申请日：2020-02-18

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Harry-Hak-Lay Chuang ,  Wei-Cheng Wu ,  Ya-Chen Kao

IPC分类号： H01L29/66 ,  H01L27/092 ,  H01L21/8238 ,  H01L21/321

摘要： A semiconductor device includes active gate structures and dummy gate electrodes. The active gate structures are above an active region of a substrate. The dummy gate electrodes are above the active region of the substrate. A number of the dummy gate electrodes is less than a number of the active gate structures. The active gate structures and the dummy gate electrodes have different materials, and a distance between adjacent one of the dummy gate electrodes and one of the active gate structures is substantially the same as a gate pitch of the active gate structures.

公开(公告)号：US11195802B2

公开(公告)日：2021-12-07

申请号：US16893440

申请日：2020-06-05

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Wei-Cheng Wu ,  Chien-Chia Chiu ,  Cheng-Hsien Hsieh ,  Li-Han Hsu ,  Meng-Tsan Lee ,  Tsung-Shu Lin

IPC分类号： H01L23/552 ,  H01L21/76 ,  H01L23/538 ,  H01L23/00 ,  H01L23/488 ,  H01L21/768 ,  H01L23/31 ,  H01L21/56

摘要： A semiconductor package includes a semiconductor die, a redistribution structure and connective terminals. The redistribution structure is disposed on the semiconductor die and includes a first metallization tier disposed in between a pair of dielectric layers. The first metallization tier includes routing conductive traces electrically connected to the semiconductor die and a shielding plate electrically insulated from the semiconductor die. The connective terminals include dummy connective terminals and active connective terminals. The dummy connective terminals are disposed on the redistribution structure and are electrically connected to the shielding plate. The active connective terminals are disposed on the redistribution structure and are electrically connected to the routing conductive traces. Vertical projections of the dummy connective terminals fall on the shielding plate.

公开(公告)号：US20210305122A1

公开(公告)日：2021-09-30

申请号：US16835322

申请日：2020-03-31

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Wei-Chih Lai ,  Chien-Chia Chiu ,  Chen-Hua Yu ,  Der-Chyang Yeh ,  Cheng-Hsien Hsieh ,  Li-Han Hsu ,  Tsung-Shu Lin ,  Wei-Cheng Wu ,  Yu-Chen Hsu

IPC分类号： H01L23/367 ,  H01L23/31 ,  H01L23/538 ,  H01L23/498 ,  H01L25/065 ,  H01L21/56 ,  H01L25/00 ,  H01L21/52

摘要： A semiconductor package includes a circuit substrate, a die, a frame structure, a heat sink lid and conductive balls. The die is disposed on a front surface of the circuit substrate and electrically connected with the circuit substrate. The die includes two first dies disposed side by side and separate from each other with a gap between two facing sidewalls of the two first dies. The frame structure is disposed on the front surface of the circuit substrate and surrounding the die. The heat sink lid is disposed on the die and the frame structure. The head sink lid has a slit that penetrates through the heat sink lid in a thickness direction and exposes the gap between the two facing sidewalls of the two first dies. The conductive balls are disposed on the opposite surface of the circuit substrate and electrically connected with the die through the circuit substrate.

公开(公告)号：US20210098391A1

公开(公告)日：2021-04-01

申请号：US16893440

申请日：2020-06-05

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Wei-Cheng Wu ,  Chien-Chia Chiu ,  Cheng-Hsien Hsieh ,  Li-Han Hsu ,  Meng-Tsan Lee ,  Tsung-Shu Lin

IPC分类号： H01L23/552 ,  H01L23/00 ,  H01L23/488 ,  H01L23/538 ,  H01L23/31 ,  H01L21/56 ,  H01L21/768

摘要： A semiconductor package includes a semiconductor die, a redistribution structure and connective terminals. The redistribution structure is disposed on the semiconductor die and includes a first metallization tier disposed in between a pair of dielectric layers. The first metallization tier includes routing conductive traces electrically connected to the semiconductor die and a shielding plate electrically insulated from the semiconductor die. The connective terminals include dummy connective terminals and active connective terminals. The dummy connective terminals are disposed on the redistribution structure and are electrically connected to the shielding plate. The active connective terminals are disposed on the redistribution structure and are electrically connected to the routing conductive traces. Vertical projections of the dummy connective terminals fall on the shielding plate.

公开(公告)号：US10783954B2

公开(公告)日：2020-09-22

申请号：US15991739

申请日：2018-05-29

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Wei-Cheng Wu ,  Chih-Yu Lin ,  Kao-Cheng Lin ,  Wei-Min Chan ,  Yen-Huei Chen

IPC分类号： G11C11/419 ,  H01L27/11 ,  G11C11/413 ,  G11C11/412

摘要： A device is disclosed that includes a plurality of first memory cells, a plurality of second memory cells, a power circuit, and a header circuit. The power circuit is configured to provide the first power voltage for the plurality of first memory cells, and to provide the second power voltage, that is independent from the first power voltage, for the plurality of second memory cells. The header circuit is configured to provide, during the write operation, the first voltage smaller than the first power voltage, the second power voltage, or smaller than the first power voltage and the second power voltage, for corresponding memory cells of the plurality of first memory cells and the plurality of second memory cells.

公开(公告)号：US10658373B2

公开(公告)日：2020-05-19

申请号：US16055357

申请日：2018-08-06

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Harry-Hak-Lay Chuang ,  Wei-Cheng Wu ,  Ya-Chen Kao

IPC分类号： H01L27/11568 ,  H01L29/66 ,  H01L27/11573 ,  H01L29/423 ,  H01L29/51 ,  H01L21/8238

摘要： A method for manufacturing a semiconductor device is provided. The method includes forming a split gate stack having a main gate and a select gate and forming a logic gate stack having a logic gate over a semiconductor substrate. The main gate and the logic gate is respectively replaced with a metal memory gate and a metal logic gate, in which the main gate and the logic gate are replaced simultaneously.

公开(公告)号：US09576645B2

公开(公告)日：2017-02-21

申请号：US14874626

申请日：2015-10-05

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Wei Min Chan ,  Wei-Cheng Wu ,  Yen-Huei Chen

IPC分类号： G11C5/06 ,  G11C11/419 ,  G11C11/412 ,  H01L27/11 ,  G11C11/413 ,  G11C8/16 ,  H01L27/06 ,  G11C5/02 ,  G11C8/08

CPC分类号： G11C11/419 ,  G11C5/025 ,  G11C8/08 ,  G11C8/16 ,  G11C11/412 ,  G11C11/413 ,  H01L27/0688 ,  H01L27/1104 ,  H01L2224/48227 ,  H01L2224/73265

摘要： A three dimensional dual-port bit cell generally comprises a first portion disposed on a first tier, wherein the first portion includes a plurality of port elements. The dual-port bit cell also includes a second portion disposed on a second tier that is vertically stacked with respect to the first tier using at least one via, wherein the second portion includes a latch.

摘要翻译： 三维双端口位单元通常包括设置在第一层上的第一部分，其中第一部分包括多个端口元件。 双端口位单元还包括设置在使用至少一个通孔相对于第一层垂直堆叠的第二层上的第二部分，其中第二部分包括闩锁。

公开(公告)号：US09159842B1

公开(公告)日：2015-10-13

申请号：US14229191

申请日：2014-03-28

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Chang-Ming Wu ,  Wei-Cheng Wu ,  Yuan-Tai Tseng ,  Shih-Chang Liu ,  Chia-Shiung Tsai ,  Ru-Liang Lee ,  Harry Hak-Lay Chuang

IPC分类号： H01L29/02 ,  H01L29/788 ,  H01L29/49 ,  H01L29/423 ,  H01L21/28 ,  H01L29/66 ,  H01L21/3205 ,  H01L21/3213 ,  H01L21/311 ,  H01L21/02

CPC分类号： H01L27/11521 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/28273 ,  H01L21/31111 ,  H01L21/32055 ,  H01L21/32133 ,  H01L21/32137 ,  H01L21/768 ,  H01L23/528 ,  H01L23/53271 ,  H01L23/5329 ,  H01L29/42328 ,  H01L29/4238 ,  H01L29/4916 ,  H01L29/6656 ,  H01L29/66825 ,  H01L29/7883 ,  H01L2924/0002 ,  H01L2924/00

摘要： A nonvolatile memory embedded in an advanced logic circuit and a method forming the same are provided. In the nonvolatile memory, the word lines and erase gates have top surfaces lower than the top surfaces of the control gate. In addition, the word lines and the erase gates are surrounded by dielectric material before a self-aligned silicidation process is performed. Therefore, no metal silicide can be formed on the word lines and the erase gate to produce problems of short circuit and current leakage in a later chemical mechanical polishing process.

摘要翻译： 提供嵌入高级逻辑电路中的非易失性存储器及其形成方法。 在非易失性存储器中，字线和擦除栅极的顶表面比控制栅极的顶表面低。 此外，在进行自对准硅化处理之前，字线和擦除栅极被电介质材料包围。 因此，在后续的化学机械抛光工艺中，字线和擦除栅极上不会形成金属硅化物，从而产生短路和漏电的问题。

公开(公告)号：US11515229B2

公开(公告)日：2022-11-29

申请号：US16835322

申请日：2020-03-31

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Wei-Chih Lai ,  Chien-Chia Chiu ,  Chen-Hua Yu ,  Der-Chyang Yeh ,  Cheng-Hsien Hsieh ,  Li-Han Hsu ,  Tsung-Shu Lin ,  Wei-Cheng Wu ,  Yu-Chen Hsu

IPC分类号： H01L23/367 ,  H01L23/31 ,  H01L25/065 ,  H01L21/56 ,  H01L23/498 ,  H01L23/538 ,  H01L21/52 ,  H01L25/00

摘要： A semiconductor package includes a circuit substrate, a die, a frame structure, a heat sink lid and conductive balls. The die is disposed on a front surface of the circuit substrate and electrically connected with the circuit substrate. The die includes two first dies disposed side by side and separate from each other with a gap between two facing sidewalls of the two first dies. The frame structure is disposed on the front surface of the circuit substrate and surrounding the die. The heat sink lid is disposed on the die and the frame structure. The head sink lid has a slit that penetrates through the heat sink lid in a thickness direction and exposes the gap between the two facing sidewalls of the two first dies. The conductive balls are disposed on the opposite surface of the circuit substrate and electrically connected with the die through the circuit substrate.

公开(公告)号：US11470720B2

公开(公告)日：2022-10-11

申请号：US17188534

申请日：2021-03-01

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Cheng-Hsien Hsieh ,  Chi-Hsi Wu ,  Chen-Hua Yu ,  Der-Chyang Yeh ,  Hsien-Wei Chen ,  Li-Han Hsu ,  Wei-Cheng Wu

IPC分类号： H05K1/11 ,  H01L23/00 ,  H05K1/18 ,  H05K1/02

摘要： A package includes a conductive pad, with a plurality of openings penetrating through the conductive pad. A dielectric layer encircles the conductive pad. The dielectric layer has portions filling the plurality of openings. An Under-Bump Metallurgy (UBM) includes a via portion extending into the dielectric layer to contact the conductive pad. A solder region is overlying and contacting the UBM. An integrated passive device is bonded to the UBM through the solder region.