公开(公告)号：US10985054B2

公开(公告)日：2021-04-20

申请号：US16927204

申请日：2020-07-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jeng-Shiou Chen ,  Chih-Yuan Ting ,  Jyu-Horng Shieh ,  Minghsing Tsai

IPC: H01L21/768 ,  H01L23/532 ,  H01L23/522 ,  H01L23/528

Abstract: An interconnect structure and a method of forming an interconnect structure are disclosed. The interconnect structure includes a lower etch stop layer (ESL); an upper low-k (LK) dielectric layer over the lower ESL; a first conductive feature in the upper LK dielectric layer, wherein the first conductive feature has a first metal line and a dummy via contiguous with the first metal line, the dummy via extending through the lower ESL; a first gap along an interface of the first conductive feature and the upper LK dielectric layer; and an upper ESL over the upper LK dielectric layer, the first conductive feature, and the first gap.

公开(公告)号：US20200286779A1

公开(公告)日：2020-09-10

申请号：US16883095

申请日：2020-05-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jeng-Shiou Chen ,  Chih-Yuan Ting

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532

Abstract: An interconnect structure and a method of forming an interconnect structure are disclosed. The interconnect structure includes a lower etch stop layer (ESL); a middle low-k (LK) dielectric layer over the lower ESL; a supporting layer over the middle LK dielectric layer; an upper LK dielectric layer over the supporting layer; an upper conductive feature in the upper LK dielectric layer, wherein the upper conductive feature is through the supporting layer; a gap along an interface of the upper conductive feature and the upper LK dielectric layer; and an upper ESL over the upper LK dielectric layer, the upper conductive feature, and the gap.

公开(公告)号：US20210366766A1

公开(公告)日：2021-11-25

申请号：US17396881

申请日：2021-08-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jeng-Shiou Chen ,  Chih-Yuan Ting

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532

Abstract: An interconnect structure and a method of forming an interconnect structure are disclosed. The interconnect structure includes a lower etch stop layer (ESL); a middle low-k (LK) dielectric layer over the lower ESL; a supporting layer over the middle LK dielectric layer; an upper LK dielectric layer over the supporting layer; an upper conductive feature in the upper LK dielectric layer, wherein the upper conductive feature is through the supporting layer; a gap along an interface of the upper conductive feature and the upper LK dielectric layer; and an upper ESL over the upper LK dielectric layer, the upper conductive feature, and the gap.

公开(公告)号：US20200343128A1

公开(公告)日：2020-10-29

申请号：US16927204

申请日：2020-07-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jeng-Shiou Chen ,  Chih-Yuan Ting ,  Jyu-Horng Shieh ,  Minghsing Tsai

IPC: H01L21/768 ,  H01L23/532 ,  H01L23/522 ,  H01L23/528

Abstract: An interconnect structure and a method of forming an interconnect structure are disclosed. The interconnect structure includes a lower etch stop layer (ESL); an upper low-k (LK) dielectric layer over the lower ESL; a first conductive feature in the upper LK dielectric layer, wherein the first conductive feature has a first metal line and a dummy via contiguous with the first metal line, the dummy via extending through the lower ESL; a first gap along an interface of the first conductive feature and the upper LK dielectric layer; and an upper ESL over the upper LK dielectric layer, the first conductive feature, and the first gap.

公开(公告)号：US11682580B2

公开(公告)日：2023-06-20

申请号：US17396881

申请日：2021-08-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jeng-Shiou Chen ,  Chih-Yuan Ting

IPC: H01L23/52 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L21/76829 ,  H01L21/7682 ,  H01L21/76831 ,  H01L21/76877 ,  H01L23/5222 ,  H01L23/5226 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/0002 ,  H01L2924/00012 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An interconnect structure and a method of forming an interconnect structure are disclosed. The interconnect structure includes a lower etch stop layer (ESL); a middle low-k (LK) dielectric layer over the lower ESL; a supporting layer over the middle LK dielectric layer; an upper LK dielectric layer over the supporting layer; an upper conductive feature in the upper LK dielectric layer, wherein the upper conductive feature is through the supporting layer; a gap along an interface of the upper conductive feature and the upper LK dielectric layer; and an upper ESL over the upper LK dielectric layer, the upper conductive feature, and the gap.

公开(公告)号：US11088021B2

公开(公告)日：2021-08-10

申请号：US16883095

申请日：2020-05-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jeng-Shiou Chen ,  Chih-Yuan Ting

IPC: H01L23/52 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532

Abstract: An interconnect structure and a method of forming an interconnect structure are disclosed. The interconnect structure includes a lower etch stop layer (ESL); a middle low-k (LK) dielectric layer over the lower ESL; a supporting layer over the middle LK dielectric layer; an upper LK dielectric layer over the supporting layer; an upper conductive feature in the upper LK dielectric layer, wherein the upper conductive feature is through the supporting layer; a gap along an interface of the upper conductive feature and the upper LK dielectric layer; and an upper ESL over the upper LK dielectric layer, the upper conductive feature, and the gap.