利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

67 条记录 (耗时 0.021 秒)

    DOUBLE PATTERNING METHOD
    4.
    发明申请
    DOUBLE PATTERNING METHOD 审中-公开

    公开(公告)号：US20200234972A1

    公开(公告)日：2020-07-23

    申请号：US16837252

    申请日：2020-04-01

    申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

    发明人： Chia-Ying Lee ,  Jyu-Horng Shieh

    IPC分类号： H01L21/311 ,  H01L21/768 ,  H01L21/033 ,  H01L21/027

    摘要： The present disclosure, in some embodiments, relates to a method of forming an integrated circuit. The method includes forming a first hard mask layer over a substrate and forming a second hard mask layer over the first hard mask layer. The second hard mask layer is patterned to define an island having a first width along a first direction. The island is patterned to form a patterned island having a second width along the first direction that is less than the first width. A sacrificial mask is formed over the first hard mask layer and the first hard mask layer is patterned according to the patterned island and the sacrificial mask.

    Semiconductor device with self aligned end-to-end conductive line structure and method for forming the same
    5.
    发明授权
    Semiconductor device with self aligned end-to-end conductive line structure and method for forming the same 有权
    具有自对准端对端导线结构的半导体器件及其形成方法

    公开(公告)号：US08962432B2

    公开(公告)日：2015-02-24

    申请号：US14161986

    申请日：2014-01-23

    申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

    发明人： Chia-Ying Lee ,  Jyu-Horng Shieh

    IPC分类号： H01L21/336 ,  H01L21/768

    CPC分类号： H01L21/76807 ,  H01L21/0337 ,  H01L21/31144 ,  H01L21/76816

    摘要： A method for forming semiconductor devices using damascene techniques provides self-aligned conductive lines that have an end-to-end spacing less than 60 nm without shorting. The method includes using at least one sacrificial hardmask layer to produce a mandrel and forming a void in the mandrel. The sacrificial hardmask layers are formed over a base material which is advantageously an insulating material. Another hardmask layer is also disposed over the base material and under the mandrel in some embodiments. Spacer material is formed alongside the mandrel and filling the void. The spacer material serves as a mask and at least one etching procedure is carried out to translate the pattern of the spacer material into the base material. The patterned base material includes trenches and raised portions. Conductive features are formed in the trenches using damascene techniques.

    摘要翻译： 使用镶嵌技术形成半导体器件的方法提供端对端间隔小于60nm而不短路的自对准导电线。 该方法包括使用至少一个牺牲硬掩模层来产生心轴并在心轴中形成空隙。 牺牲硬掩模层形成在有利地是绝缘材料的基材上。 在一些实施例中，另一个硬掩模层也设置在基体材料上并在心轴下方。 垫片材料沿心轴形成并填充空隙。 间隔材料用作掩模，并且执行至少一个蚀刻程序以将间隔物材料的图案转化为基底材料。 图案化的基材包括沟槽和凸起部分。 使用镶嵌技术在沟槽中形成导电特征。

    DOUBLE PATTERNING METHOD
    6.
    发明申请
    DOUBLE PATTERNING METHOD 有权
    双重图案方法

    公开(公告)号：US20140273433A1

    公开(公告)日：2014-09-18

    申请号：US13920201

    申请日：2013-06-18

    申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

    发明人： Chia-Ying Lee ,  Jyu-Horng Shieh

    IPC分类号： H01L21/027 ,  H01L21/768 ,  H01L21/311

    CPC分类号： H01L21/31144 ,  H01L21/027 ,  H01L21/0337 ,  H01L21/76816 ,  H01L21/76832 ,  H01L21/76883

    摘要： Self-aligned double patterning methods that can be used in back-end-of-line (BEOL) processing and other stages of integrate circuit device manufacturing. In these methods, line termini are masked prior to self-aligned double patterning. The self-aligned double patterning involves forming a mandrel, the shape of which is determined by a lithographic mask. That same lithographic mask is used prior to self-aligned double patterning to trim the mask that determines the locations of line termini. The methods provide precise positioning of the line termini mask relative to the line locations determined by self-aligned double patterning. The methods forms consistent end-of-line shapes and allow line termini to be placed more closely together than would otherwise be feasible.

    摘要翻译： 自对准双重图案化方法，可用于后端行（BEOL）处理和集成电路器件制造的其他阶段。 在这些方法中，在自对准双重图案化之前掩蔽线末端。 自对准双图案包括形成心轴，其形状由光刻掩模确定。 在自对准双重图案化之前使用相同的光刻掩模来修整确定线末端位置的掩模。 该方法提供线路终端掩模相对于通过自对准双重图案化确定的线路位置的精确定位。 这些方法形成一致的行尾形状，并允许线路终端与其他情况相比更紧密地放置在一起。

    DUAL DAMASCENE PROCESS
    7.
    发明申请
    DUAL DAMASCENE PROCESS 有权
    双重加工过程

    公开(公告)号：US20140127897A1

    公开(公告)日：2014-05-08

    申请号：US14152093

    申请日：2014-01-10

    申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

    发明人： Chia-Ying LEE ,  Jyu-Horng Shieh

    IPC分类号： H01L21/768

    CPC分类号： H01L21/76879 ,  H01L21/31144 ,  H01L21/76807 ,  H01L21/76811 ,  H01L21/76813 ,  H01L21/76816

    摘要： A method for forming dual damascene structures in a semiconductor structure is disclosed. The method generally includes etching a substrate using a first hard mask to form a plurality of first trenches and vias, forming a set of first conductive lines and via interconnects, removing the first hard mask, etching the substrate using a second hard mask to form a plurality of second trenches and vias, and forming a set of second conductive lines and via interconnects. At least some of the first conductive lines are interspersed between some of the second conductive lines. A planarization process is used on the substrate after forming the first conductive lines and via interconnects before forming the second conductive lines and via interconnects.

    摘要翻译： 公开了一种在半导体结构中形成双镶嵌结构的方法。 该方法通常包括使用第一硬掩模蚀刻衬底以形成多个第一沟槽和通孔，形成一组第一导电线和通孔互连，去除第一硬掩模，使用第二硬掩模蚀刻衬底以形成 多个第二沟槽和通孔，以及形成一组第二导线和通孔互连。 至少一些第一导电线分散在一些第二导线之间。 在形成第一导电线之后，在形成第二导线之间并通过互连件之间经由互连，在衬底上使用平坦化工艺。

    Gradient protection layer in MTJ manufacturing
    10.
    发明授权
    Gradient protection layer in MTJ manufacturing 有权

    公开(公告)号：US11856865B2

    公开(公告)日：2023-12-26

    申请号：US17869335

    申请日：2022-07-20

    申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

    发明人： Tai-Yen Peng ,  Yu-Shu Chen ,  Sin-Yi Yang ,  Chen-Jung Wang ,  Chien Chung Huang ,  Han-Ting Lin ,  Jyu-Horng Shieh ,  Qiang Fu

    IPC分类号： H10N50/01 ,  H10N50/80

    CPC分类号： H10N50/01 ,  H10N50/80

    摘要： A method includes forming Magnetic Tunnel Junction (MTJ) stack layers, which includes depositing a bottom electrode layer; depositing a bottom magnetic electrode layer over the bottom electrode layer; depositing a tunnel barrier layer over the bottom magnetic electrode layer; depositing a top magnetic electrode layer over the tunnel barrier layer; and depositing a top electrode layer over the top magnetic electrode layer. The method further includes patterning the MTJ stack layers to form a MTJ; and performing a passivation process on a sidewall of the MTJ to form a protection layer. The passivation process includes reacting sidewall surface portions of the MTJ with a process gas comprising elements selected from the group consisting of oxygen, nitrogen, carbon, and combinations thereof.