公开(公告)号：US11714951B2

公开(公告)日：2023-08-01

申请号：US17386737

申请日：2021-07-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Ming Chang ,  Shinn-Sheng Yu ,  Jue-Chin Yu ,  Ping-Chieh Wu

IPC: G06F30/30 ,  G03F7/20 ,  G03F1/36 ,  G06F30/398 ,  G03F7/00

CPC classification number: G06F30/398 ,  G03F1/36 ,  G03F7/70433

Abstract: A method includes generating a diffraction map from a plurality of target patterns, generating a favorable zone and an unfavorable zone from the diffraction map, placing a plurality of sub-resolution patterns in the favorable zone, and performing a plurality of geometric operations on the plurality of sub-resolution patterns to generate modified sub-resolution patterns. The modified sub-resolution patterns extend into the favorable zone, and are away from the unfavorable zone.

公开(公告)号：US12019974B2

公开(公告)日：2024-06-25

申请号：US18334551

申请日：2023-06-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Ming Chang ,  Shinn-Sheng Yu ,  Jue-Chin Yu ,  Ping-Chieh Wu

IPC: G06F30/30 ,  G03F1/36 ,  G03F7/00 ,  G06F30/398

CPC classification number: G06F30/398 ,  G03F1/36 ,  G03F7/70433

Abstract: A method includes generating a diffraction map from a plurality of target patterns, generating a favorable zone and an unfavorable zone from the diffraction map, placing a plurality of sub-resolution patterns in the favorable zone, and performing a plurality of geometric operations on the plurality of sub-resolution patterns to generate modified sub-resolution patterns. The modified sub-resolution patterns extend into the favorable zone, and are away from the unfavorable zone.

公开(公告)号：US20220365419A1

公开(公告)日：2022-11-17

申请号：US17386737

申请日：2021-07-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Ming Chang ,  Shinn-Sheng Yu ,  Jue-Chin Yu ,  Ping-Chieh Wu

IPC: G03F1/36 ,  G03F7/20 ,  H01L21/027

Abstract: A method includes generating a diffraction map from a plurality of target patterns, generating a favorable zone and an unfavorable zone from the diffraction map, placing a plurality of sub-resolution patterns in the favorable zone, and performing a plurality of geometric operations on the plurality of sub-resolution patterns to generate modified sub-resolution patterns. The modified sub-resolution patterns extend into the favorable zone, and are away from the unfavorable zone.

公开(公告)号：US20240311545A1

公开(公告)日：2024-09-19

申请号：US18672836

申请日：2024-05-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Ming Chang ,  Shinn-Sheng Yu ,  Jue-Chin Yu ,  Ping-Chieh Wu

IPC: G06F30/398 ,  G03F1/36 ,  G03F7/00

CPC classification number: G06F30/398 ,  G03F1/36 ,  G03F7/70433

Abstract: A method includes generating a diffraction map from a plurality of target patterns, generating a favorable zone and an unfavorable zone from the diffraction map, placing a plurality of sub-resolution patterns in the favorable zone, and performing a plurality of geometric operations on the plurality of sub-resolution patterns to generate modified sub-resolution patterns. The modified sub-resolution patterns extend into the favorable zone, and are away from the unfavorable zone.

公开(公告)号：US20230325579A1

公开(公告)日：2023-10-12

申请号：US18334551

申请日：2023-06-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Ming Chang ,  Shinn-Sheng Yu ,  Jue-Chin Yu ,  Ping-Chieh Wu

IPC: G06F30/398 ,  G03F1/36 ,  G03F7/20

CPC classification number: G06F30/398 ,  G03F7/70433 ,  G03F1/36

Abstract: A method includes generating a diffraction map from a plurality of target patterns, generating a favorable zone and an unfavorable zone from the diffraction map, placing a plurality of sub-resolution patterns in the favorable zone, and performing a plurality of geometric operations on the plurality of sub-resolution patterns to generate modified sub-resolution patterns. The modified sub-resolution patterns extend into the favorable zone, and are away from the unfavorable zone.

公开(公告)号：US11092899B2

公开(公告)日：2021-08-17

申请号：US16698044

申请日：2019-11-27

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Hsu-Ting Huang ,  Tung-Chin Wu ,  Shih-Hsiang Lo ,  Chih-Ming Lai ,  Jue-Chin Yu ,  Ru-Gun Liu ,  Chin-Hsiang Lin

IPC: G06F30/398 ,  G06F30/392 ,  G03F7/20 ,  G06F16/23 ,  G06N3/08 ,  G06N3/04

Abstract: A method for manufacturing a lithographic mask for an integrated circuit includes performing an optical proximity correction (OPC) process to an integrated circuit mask layout to produce a corrected mask layout. The method further includes performing an inverse lithographic technology (ILT) process to the corrected mask layout to enhance the corrected mask layout to produce an OPC-ILT-enhanced mask layout. The method also includes performing an inverse lithographic technology (ILT) process to the corrected mask layout to enhance the corrected mask layout to produce an OPC-ILT-enhanced mask layout.