公开(公告)号：US20240387731A1

公开(公告)日：2024-11-21

申请号：US18784144

申请日：2024-07-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chien-Wei Lee ,  Hsueh-Chang Sung ,  Yen-Ru Lee ,  Jyun-Chih Lin ,  Tzu-Hsiang Hsu ,  Feng-Cheng Yang

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/66

Abstract: A semiconductor device including a source/drain region having a V-shaped bottom surface and extending below gate spacers adjacent a gate stack and a method of forming the same are disclosed. In an embodiment, a method includes forming a gate stack over a fin; forming a gate spacer on a sidewall of the gate stack; etching the fin with a first anisotropic etch process to form a first recess adjacent the gate spacer; etching the fin with a second etch process using etchants different from the first etch process to remove an etching residue from the first recess; etching surfaces of the first recess with a third anisotropic etch process using etchants different from the first etch process to form a second recess extending below the gate spacer and having a V-shaped bottom surface; and epitaxially forming a source/drain region in the second recess.

公开(公告)号：US20230275153A1

公开(公告)日：2023-08-31

申请号：US18311016

申请日：2023-05-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chien-Wei Lee ,  Hsueh-Chang Sung ,  Yen-Ru Lee ,  Jyun-Chih Lin ,  Tzu-Hsiang Hsu ,  Feng-Cheng Yang

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/66

CPC classification number: H01L29/785 ,  H01L29/0847 ,  H01L29/66545 ,  H01L29/6681

Abstract: A semiconductor device including a source/drain region having a V-shaped bottom surface and extending below gate spacers adjacent a gate stack and a method of forming the same are disclosed. In an embodiment, a method includes forming a gate stack over a fin; forming a gate spacer on a sidewall of the gate stack; etching the fin with a first anisotropic etch process to form a first recess adjacent the gate spacer; etching the fin with a second etch process using etchants different from the first etch process to remove an etching residue from the first recess; etching surfaces of the first recess with a third anisotropic etch process using etchants different from the first etch process to form a second recess extending below the gate spacer and having a V-shaped bottom surface; and epitaxially forming a source/drain region in the second recess.

公开(公告)号：US11677027B2

公开(公告)日：2023-06-13

申请号：US17371953

申请日：2021-07-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chien-Wei Lee ,  Hsueh-Chang Sung ,  Yen-Ru Lee ,  Jyun-Chih Lin ,  Tzu-Hsiang Hsu ,  Feng-Cheng Yang

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/66

CPC classification number: H01L29/785 ,  H01L29/0847 ,  H01L29/6681 ,  H01L29/66545

Abstract: A semiconductor device including a source/drain region having a V-shaped bottom surface and extending below gate spacers adjacent a gate stack and a method of forming the same are disclosed. In an embodiment, a method includes forming a gate stack over a fin; forming a gate spacer on a sidewall of the gate stack; etching the fin with a first anisotropic etch process to form a first recess adjacent the gate spacer; etching the fin with a second etch process using etchants different from the first etch process to remove an etching residue from the first recess; etching surfaces of the first recess with a third anisotropic etch process using etchants different from the first etch process to form a second recess extending below the gate spacer and having a V-shaped bottom surface; and epitaxially forming a source/drain region in the second recess.

公开(公告)号：US20210336048A1

公开(公告)日：2021-10-28

申请号：US17371953

申请日：2021-07-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chien-Wei Lee ,  Hsueh-Chang Sung ,  Yen-Ru Lee ,  Jyun-Chih Lin ,  Tzu-Hsiang Hsu ,  Feng-Cheng Yang

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/08

Abstract: A semiconductor device including a source/drain region having a V-shaped bottom surface and extending below gate spacers adjacent a gate stack and a method of forming the same are disclosed. In an embodiment, a method includes forming a gate stack over a fin; forming a gate spacer on a sidewall of the gate stack; etching the fin with a first anisotropic etch process to form a first recess adjacent the gate spacer; etching the fin with a second etch process using etchants different from the first etch process to remove an etching residue from the first recess; etching surfaces of the first recess with a third anisotropic etch process using etchants different from the first etch process to form a second recess extending below the gate spacer and having a V-shaped bottom surface; and epitaxially forming a source/drain region in the second recess.