公开(公告)号：US20230411277A1

公开(公告)日：2023-12-21

申请号：US17842972

申请日：2022-06-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Hsien Lin ,  Hsing-Chih Lin ,  Ke Chun Liu ,  Min-Feng Kao ,  Kuan-Hua Lin

IPC: H01L23/522 ,  G06F30/392 ,  H01L49/02

CPC classification number: H01L23/5223 ,  H01L23/5226 ,  G06F30/392 ,  H01L28/91

Abstract: Capacitors and interconnect structures that couple transistors to one another include parallel stacked metal lines separated by dielectric layers. When capacitors and interconnect structures are combined, each top metal capacitor plate can be coupled to the nearest upper metal line by a through-via, while each bottom metal capacitor plate can be coupled directly to the nearest lower metal line without a via. When a back end of line (BEOL) cell includes multiple capacitors, and design rules require shrinking the cell dimensions, substituting an alternative design that has fewer through-vias can facilitate compaction of the BEOL cell. Similarly, placing capacitors in close proximity so that they can share through-vias can allow even further compaction.