公开(公告)号：US20250157889A1

公开(公告)日：2025-05-15

申请号：US18582326

申请日：2024-02-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Chieh Chang ,  Chih Hsin Yang ,  Mao-Nan Wang ,  Kuan-Hsun Wang ,  Yang-Hsin Shih ,  Yun-Sheng Li ,  Liang-Wei Wang ,  Dian-Hau Chen

IPC: H01L23/48 ,  H01L21/768 ,  H01L23/00 ,  H01L23/31

Abstract: A method includes forming a first device die comprising forming an integrated circuit on a semiconductor substrate; and forming an interconnect structure on the semiconductor substrate. The interconnect structure has a plurality of metal layers. The method further includes bonding a second device die to the first device die, and forming gap-fill regions surrounding the second device die. In a first formation process, a first TSV is formed to penetrate through the semiconductor substrate, wherein the first TSV has a first width. In a second formation process, a second TSV is formed to penetrate through the semiconductor substrate. The second TSV has a second width different from the first width.

公开(公告)号：US20250069990A1

公开(公告)日：2025-02-27

申请号：US18403146

申请日：2024-01-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yang-Hsin Shih ,  Kuan-Hsun Wang ,  Chih Hsin Yang

IPC: H01L23/48 ,  H01L21/768 ,  H01L23/00 ,  H01L23/522 ,  H01L23/58

Abstract: An embodiment includes a device, the device including a first die including a first surface and a second surface opposite the first surface. The first die includes a plurality of through substrate vias (TSVs) exposed from the second surface of the first die. The device also includes a guard ring surrounding the plurality of TSVs. The device also includes a dummy metallization pattern surrounding the guard ring. The device also includes an active metallization pattern connected to active devices in the first die.

公开(公告)号：US20250070052A1

公开(公告)日：2025-02-27

申请号：US18493187

申请日：2023-10-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ke-Gang Wen ,  Chih Hsin Yang ,  Kuan-Hsun Wang ,  Tsung-Chieh Hsiao ,  Liang-Wei Wang ,  Dian-Hau Chen

IPC: H01L23/00 ,  H01L21/78 ,  H01L23/544 ,  H01L23/58 ,  H01L29/66

Abstract: A method includes forming first nanostructures over a first region of a substrate; forming second nanostructures over a second region of the substrate; forming first gate structures around the first nanostructures; replacing the second nanostructures with isolation regions; and forming a seal ring over the substrate, wherein the seal ring is between the first region and the second region.