公开(公告)号：US20250157889A1

公开(公告)日：2025-05-15

申请号：US18582326

申请日：2024-02-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Chieh Chang ,  Chih Hsin Yang ,  Mao-Nan Wang ,  Kuan-Hsun Wang ,  Yang-Hsin Shih ,  Yun-Sheng Li ,  Liang-Wei Wang ,  Dian-Hau Chen

IPC: H01L23/48 ,  H01L21/768 ,  H01L23/00 ,  H01L23/31

Abstract: A method includes forming a first device die comprising forming an integrated circuit on a semiconductor substrate; and forming an interconnect structure on the semiconductor substrate. The interconnect structure has a plurality of metal layers. The method further includes bonding a second device die to the first device die, and forming gap-fill regions surrounding the second device die. In a first formation process, a first TSV is formed to penetrate through the semiconductor substrate, wherein the first TSV has a first width. In a second formation process, a second TSV is formed to penetrate through the semiconductor substrate. The second TSV has a second width different from the first width.