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公开(公告)号：US09000823B2
公开(公告)日：2015-04-07
申请号：US14024660
申请日：2013-09-12
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Mu-Shan Lin
CPC classification number: H03K5/01 , H03K5/06 , H03K2005/00156 , H03L7/00
Abstract: An integrated circuit includes a clock source tier and at least two clock tree tiers disposed in a vertical stack with the clock source tier. The clock source tier includes a clock circuit, and each of the at least two clock tree tiers includes a clock tree circuit. The clock circuit is disposed in the clock source tier is coupled to the clock tree circuits disposed in the at least two clock tree tiers by at least one inter-layer via.
Abstract translation: 集成电路包括时钟源层和至少两个时钟树层，其布置在具有时钟源层的垂直堆叠中。 时钟源层包括时钟电路，并且至少两个时钟树层中的每一个包括时钟树电路。 设置在时钟源层中的时钟电路通过至少一个层间通孔耦合到设置在至少两个时钟树层中的时钟树电路。
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Patent Agency Ranking
公开(公告)号：US10277215B2
公开(公告)日：2019-04-30
申请号：US15581033
申请日：2017-04-28
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Meng-Ting Tsai , Chien-Chun Tsai , Mu-Shan Lin , Wen-Hung Huang , Yu-Chi Chen
Abstract: Digital controlled delay lines are provided. A digital controlled delay line includes a plurality of delay cells coupled in a chain forming a propagation path to propagate an input signal and to delay the input signal by a delay time. The propagation path is formed when a single delay cell is operated in a feedback mode, the delay cells previous to the single delay cell in the chain are operated in a propagation mode, a subsequent delay cell following the single delay cell in the chain is operated in a standby mode, and the delay cells following the first subsequent delay cell in the chain are operated in an idle mode.
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公开(公告)号：US09571073B2
公开(公告)日：2017-02-14
申请号：US14636224
申请日：2015-03-03
Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Inventor： Mu-Shan Lin
CPC classification number: H03K5/01 , H03K5/06 , H03K2005/00156 , H03L7/00
Abstract: An integrated circuit includes a clock source tier and at least two clock distribution tiers disposed in a vertical stack with the clock source tier. The clock source tier includes a clock circuit. Each of the at least two clock distribution tiers includes a clock distribution circuit. Each clock distribution circuit includes at least one pair of cross-coupled inverters.
Abstract translation: 集成电路包括时钟源层和至少两个时钟分配层，其布置在与时钟源层的垂直堆叠中。 时钟源层包括时钟电路。 所述至少两个时钟分配层中的每一个包括时钟分配电路。 每个时钟分配电路包括至少一对交叉耦合的反相器。
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公开(公告)号：US10164758B2
公开(公告)日：2018-12-25
申请号：US15386342
申请日：2016-12-21
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Shu-Chun Yang , Mu-Shan Lin , Wen-Hung Huang
Abstract: An electronic system includes transmitting circuitry of a first clock domain and receiving circuitry of a second domain. The transmitting circuitry re-times a digital input signal with rising edges of a clocking signal of the first clock domain when a phase of the clocking signal of the first clock domain leads a phase of a clocking signal associated with the digital input signal. Otherwise, the transmitting circuitry re-times the digital input signal with falling edges of the clocking signal of the first clock domain when the phase of the clocking signal of the first clock domain does not lead the phase of the clocking signal associated with a digital input signal. The receiving circuitry receives the re-timed digital input signal from the transmitting circuitry. Thereafter, the receiving circuitry re-times the re-timed digital input signal with rising edges of a phase of a clocking signal associated with the re-timed digital input signal when the phase of the clocking signal associated with the re-timed digital input signal leads a phase of a clocking signal of the second clock domain. Otherwise, the receiving circuitry re-times the re-timed digital input signal with falling edges of the phase of a clocking signal associated with the re-timed digital input signal when the phase of the clocking signal associated with the re-timed digital input signal does not lead the phase of a clocking signal of the second clock domain.
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公开(公告)号：US20180152279A1
公开(公告)日：2018-05-31
申请号：US15386342
申请日：2016-12-21
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Shu-Chun YANG , Mu-Shan Lin , Wen-Hung Huang
IPC: H04L7/00
CPC classification number: H04L7/0008 , G06F13/00 , H04L7/0045 , H04L7/0091
Abstract: An electronic system includes transmitting circuitry of a first clock domain and receiving circuitry of a second domain. The transmitting circuitry re-times a digital input signal with rising edges of a clocking signal of the first clock domain when a phase of the clocking signal of the first clock domain leads a phase of a clocking signal associated with the digital input signal. Otherwise, the transmitting circuitry re-times the digital input signal with falling edges of the clocking signal of the first clock domain when the phase of the clocking signal of the first clock domain does not lead the phase of the clocking signal associated with a digital input signal. The receiving circuitry receives the re-timed digital input signal from the transmitting circuitry. Thereafter, the receiving circuitry re-times the re-timed digital input signal with rising edges of a phase of a clocking signal associated with the re-timed digital input signal when the phase of the clocking signal associated with the re-timed digital input signal leads a phase of a clocking signal of the second clock domain. Otherwise, the receiving circuitry re-times the re-timed digital input signal with falling edges of the phase of a clocking signal associated with the re-timed digital input signal when the phase of the clocking signal associated with the re-timed digital input signal does not lead the phase of a clocking signal of the second clock domain.
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公开(公告)号：US20150070067A1
公开(公告)日：2015-03-12
申请号：US14024660
申请日：2013-09-12
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Mu-Shan Lin
IPC: H03K5/01
CPC classification number: H03K5/01 , H03K5/06 , H03K2005/00156 , H03L7/00
Abstract: An integrated circuit includes a clock source tier and at least two clock tree tiers disposed in a vertical stack with the clock source tier. The clock source tier includes a clock circuit, and each of the at least two clock tree tiers includes a clock tree circuit. The clock circuit is disposed in the clock source tier is coupled to the clock tree circuits disposed in the at least two clock tree tiers by at least one inter-layer via.
Abstract translation: 集成电路包括时钟源层和至少两个时钟树层，其布置在具有时钟源层的垂直堆叠中。 时钟源层包括时钟电路，并且至少两个时钟树层中的每一个包括时钟树电路。 设置在时钟源层中的时钟电路通过至少一个层间通孔耦合到设置在至少两个时钟树层中的时钟树电路。
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