公开(公告)号：US11984883B2

公开(公告)日：2024-05-14

申请号：US17543554

申请日：2021-12-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tsung-Hsin Yu ,  Nick Pai ,  Bo-Ting Chen

IPC: H03K17/16 ,  H03K19/003 ,  H03K19/0175

CPC classification number: H03K17/162 ,  H03K19/00361 ,  H03K19/017509

Abstract: Circuits and methods for preventing glitch in a circuit are disclosed. In one example, a circuit coupled to an input/output pad is disclosed. The circuit includes: a first level shifter, a second level shifter, and a control logic circuit. The first level shifter is configured for generating a data signal. The second level shifter is configured for generating an output enable signal. The first and second level shifters are controlled by first and second power-on-control signals, respectively. The control logic circuit is coupled to the first level shifter and the second level shifter.

公开(公告)号：US20220094351A1

公开(公告)日：2022-03-24

申请号：US17543554

申请日：2021-12-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tsung-Hsin YU ,  Nick Pai ,  Bo-Ting Chen

IPC: H03K17/16 ,  H03K19/003

Abstract: Circuits and methods for preventing glitch in a circuit are disclosed. In one example, a circuit coupled to an input/output pad is disclosed. The circuit includes: a first level shifter, a second level shifter, and a control logic circuit. The first level shifter is configured for generating a data signal. The second level shifter is configured for generating an output enable signal. The first and second level shifters are controlled by first and second power-on-control signals, respectively. The control logic circuit is coupled to the first level shifter and the second level shifter.

公开(公告)号：US11223350B2

公开(公告)日：2022-01-11

申请号：US16901418

申请日：2020-06-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tsung-Hsin Yu ,  Nick Pai ,  Bo-Ting Chen

IPC: H03K17/16 ,  H03K19/003 ,  H03K19/0175

Abstract: Circuits and methods for preventing glitch in a circuit are disclosed. In one example, a circuit coupled to an input/output pad is disclosed. The circuit includes: a first level shifter, a second level shifter, and a control logic circuit. The first level shifter is configured for generating a data signal. The second level shifter is configured for generating an output enable signal. The first and second level shifters are controlled by first and second power-on-control signals, respectively. The control logic circuit is coupled to the first level shifter and the second level shifter.

公开(公告)号：US10686438B2

公开(公告)日：2020-06-16

申请号：US15965875

申请日：2018-04-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tsung-Hsin Yu ,  Nick Pai ,  Bo-Ting Chen

IPC: H03K17/16 ,  H03K19/003

Abstract: Circuits and methods for preventing glitch in a circuit are disclosed. In one example, a circuit coupled to an input/output pad is disclosed. The circuit includes: a first level shifter, a second level shifter, and a control logic circuit. The first level shifter is configured for generating a data signal. The second level shifter is configured for generating an output enable signal. The first and second level shifters are controlled by first and second power-on-control signals, respectively. The control logic circuit is coupled to the first level shifter and the second level shifter, and configured for driving the input/output pad to a voltage level based on the data signal and the output enable signal.