公开(公告)号：US10483973B2

公开(公告)日：2019-11-19

申请号：US16156507

申请日：2018-10-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Hui Chen ,  Wan-Yen Lin ,  Tsung-Hsin Yu

IPC: H03K19/003 ,  H03K17/00 ,  H03K3/356

Abstract: A circuit includes: a first type of swing reduction circuit coupled between an input/output pad and a buffer circuit; and a second type of swing reduction circuit coupled between the input/output pad and the buffer circuit, wherein the first type of swing reduction circuit is configured to increase a voltage received by respective gates of a first subset of transistors of the buffer circuit when a voltage applied on the input/output pad is equal to a first supply voltage, and the second type of swing reduction circuit is configured to reduce a voltage received by respective gates of a second subset of transistors of the buffer circuit when the voltage applied on the input/output pad is equal to a second supply voltage.

公开(公告)号：US12159904B2

公开(公告)日：2024-12-03

申请号：US17523033

申请日：2021-11-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Chung Chen ,  Tsung-Hsin Yu ,  Chung-Hui Chen ,  Hui-Zhong Zhuang ,  Ya Yun Liu

IPC: H01L29/10 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/08

Abstract: The present disclosure describes structure with a substrate, a first well region, a second well region, and a third well region. The first well region is in the substrate. The second well region is in the first well region and includes a first source/drain (S/D) region. The third well region is in the substrate and adjacent to the first well region. The third well region includes a second S/D region, where a spacing between the first and second S/D regions is less than about 3 μm.

公开(公告)号：US20200052699A1

公开(公告)日：2020-02-13

申请号：US16654677

申请日：2019-10-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Hui Chen ,  Wan-Yen Lin ,  Tsung-Hsin Yu

IPC: H03K19/003 ,  H03K3/356

Abstract: A circuit includes: a first swing reduction circuit coupled between an input/output pad and a buffer circuit, and a second swing reduction circuit coupled between the input/output pad and the buffer circuit. The first swing reduction circuit comprises a first transistor gated by a first bias voltage and comprises a second transistor drained by the first bias voltage. The first swing reduction circuit is configured to increase a voltage at a first node in the buffer circuit when a voltage applied on the input/output pad is equal to a first supply voltage. The second swing reduction circuit is configured to reduce a voltage at a second node in the buffer circuit when the voltage applied on the input/output pad is equal to a second supply voltage.

公开(公告)号：US11223350B2

公开(公告)日：2022-01-11

申请号：US16901418

申请日：2020-06-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tsung-Hsin Yu ,  Nick Pai ,  Bo-Ting Chen

IPC: H03K17/16 ,  H03K19/003 ,  H03K19/0175

Abstract: Circuits and methods for preventing glitch in a circuit are disclosed. In one example, a circuit coupled to an input/output pad is disclosed. The circuit includes: a first level shifter, a second level shifter, and a control logic circuit. The first level shifter is configured for generating a data signal. The second level shifter is configured for generating an output enable signal. The first and second level shifters are controlled by first and second power-on-control signals, respectively. The control logic circuit is coupled to the first level shifter and the second level shifter.

公开(公告)号：US10756735B2

公开(公告)日：2020-08-25

申请号：US16654677

申请日：2019-10-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Hui Chen ,  Wan-Yen Lin ,  Tsung-Hsin Yu

IPC: H03K19/003 ,  H03K17/00 ,  H03K3/356

Abstract: A circuit includes: a first swing reduction circuit coupled between an input/output pad and a buffer circuit, and a second swing reduction circuit coupled between the input/output pad and the buffer circuit. The first swing reduction circuit comprises a first transistor gated by a first bias voltage and comprises a second transistor drained by the first bias voltage. The first swing reduction circuit is configured to increase a voltage at a first node in the buffer circuit when a voltage applied on the input/output pad is equal to a first supply voltage. The second swing reduction circuit is configured to reduce a voltage at a second node in the buffer circuit when the voltage applied on the input/output pad is equal to a second supply voltage.

公开(公告)号：US10686438B2

公开(公告)日：2020-06-16

申请号：US15965875

申请日：2018-04-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tsung-Hsin Yu ,  Nick Pai ,  Bo-Ting Chen

IPC: H03K17/16 ,  H03K19/003

Abstract: Circuits and methods for preventing glitch in a circuit are disclosed. In one example, a circuit coupled to an input/output pad is disclosed. The circuit includes: a first level shifter, a second level shifter, and a control logic circuit. The first level shifter is configured for generating a data signal. The second level shifter is configured for generating an output enable signal. The first and second level shifters are controlled by first and second power-on-control signals, respectively. The control logic circuit is coupled to the first level shifter and the second level shifter, and configured for driving the input/output pad to a voltage level based on the data signal and the output enable signal.

公开(公告)号：US11190187B2

公开(公告)日：2021-11-30

申请号：US17001022

申请日：2020-08-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Hui Chen ,  Wan-Yen Lin ,  Tsung-Hsin Yu

IPC: H03K19/003 ,  H03K17/00 ,  H03K3/356

Abstract: A circuit includes: a first swing reduction circuit coupled between an input/output pad and a buffer circuit, and a second swing reduction circuit coupled between the input/output pad and the buffer circuit. The first swing reduction circuit comprises a first transistor gated by a first bias voltage and comprises a second transistor drained by the first bias voltage. The first swing reduction circuit is configured to increase a voltage at a first node in the buffer circuit when a voltage applied on the input/output pad is equal to a first supply voltage. The second swing reduction circuit is configured to reduce a voltage at a second node in the buffer circuit when the voltage applied on the input/output pad is equal to a second supply voltage.

公开(公告)号：US11984883B2

公开(公告)日：2024-05-14

申请号：US17543554

申请日：2021-12-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tsung-Hsin Yu ,  Nick Pai ,  Bo-Ting Chen

IPC: H03K17/16 ,  H03K19/003 ,  H03K19/0175

CPC classification number: H03K17/162 ,  H03K19/00361 ,  H03K19/017509

Abstract: Circuits and methods for preventing glitch in a circuit are disclosed. In one example, a circuit coupled to an input/output pad is disclosed. The circuit includes: a first level shifter, a second level shifter, and a control logic circuit. The first level shifter is configured for generating a data signal. The second level shifter is configured for generating an output enable signal. The first and second level shifters are controlled by first and second power-on-control signals, respectively. The control logic circuit is coupled to the first level shifter and the second level shifter.

公开(公告)号：US20220367637A1

公开(公告)日：2022-11-17

申请号：US17523033

申请日：2021-11-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Chung Chen ,  Tsung-Hsin Yu ,  Chung-Hui Chen ,  Hui-Zhong Zhuang ,  Ya Yun Liu

IPC: H01L29/10 ,  H01L27/088 ,  H01L29/08 ,  H01L21/8234

Abstract: The present disclosure describes structure with a substrate, a first well region, a second well region, and a third well region. The first well region is in the substrate. The second well region is in the first well region and includes a first source/drain (S/D) region. The third well region is in the substrate and adjacent to the first well region. The third well region includes a second S/D region, where a spacing between the first and second S/D regions is less than about 3 μm.

公开(公告)号：US20190173471A1

公开(公告)日：2019-06-06

申请号：US16156507

申请日：2018-10-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Hui Chen ,  Wan-Yen Lin ,  Tsung-Hsin Yu

IPC: H03K19/003 ,  H03K3/356

Abstract: A circuit includes: a first type of swing reduction circuit coupled between an input/output pad and a buffer circuit; and a second type of swing reduction circuit coupled between the input/output pad and the buffer circuit, wherein the first type of swing reduction circuit is configured to increase a voltage received by respective gates of a first subset of transistors of the buffer circuit when a voltage applied on the input/output pad is equal to a first supply voltage, and the second type of swing reduction circuit is configured to reduce a voltage received by respective gates of a second subset of transistors of the buffer circuit when the voltage applied on the input/output pad is equal to a second supply voltage.