公开(公告)号：US10534393B2

公开(公告)日：2020-01-14

申请号：US16106476

申请日：2018-08-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yvonne Lin ,  Da-Wen Lin ,  Peter Huang ,  Paul Rousseau ,  Sheng-Jier Yang

IPC: H01L29/78 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/66 ,  G05F3/16 ,  G05F1/46 ,  G05F1/595 ,  G05F3/24

Abstract: Some embodiments relate to a method. A semiconductor substrate is provided and has a base region and a crown structure extending upwardly from the base region. A plurality of fins are formed to extend upwardly from an upper surface of the crown structure. A gate dielectric material is formed over upper surfaces and sidewalls of the plurality of the fins. A conductive electrode material is formed over upper surfaces and sidewalls of the gate dielectric material. An etch is performed to etch back the conductive electrode material so upper surfaces of etched back conductive electrodes reside below the upper surfaces of the plurality of fins.

公开(公告)号：US11150680B2

公开(公告)日：2021-10-19

申请号：US16578361

申请日：2019-09-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yvonne Lin ,  Da-Wen Lin ,  Peter Huang ,  Paul Rousseau ,  Sheng-Jier Yang

IPC: H01L29/78 ,  H01L29/66 ,  H01L27/088 ,  H01L29/06 ,  H01L21/8234 ,  G05F3/16 ,  G05F1/46 ,  G05F1/595 ,  G05F3/24

Abstract: Some embodiments relate to a device disposed on a semiconductor substrate. The semiconductor substrate includes a base region and a crown structure extending upwardly from the base region. The crown structure is narrower than the base region. A plurality of fins extend upwardly from an upper surface of the crown structure. A gate dielectric material is disposed over upper surfaces and sidewalls of the plurality of the fins. A conductive electrode is disposed along sidewall portions of the gate dielectric material. An uppermost surface of the conductive electrode resides below the upper surfaces of the plurality of fins.

公开(公告)号：US20200019201A1

公开(公告)日：2020-01-16

申请号：US16578361

申请日：2019-09-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yvonne Lin ,  Da-Wen Lin ,  Peter Huang ,  Paul Rousseau ,  Sheng-Jier Yang

IPC: G05F3/16 ,  H01L29/06 ,  H01L27/088 ,  H01L21/8234 ,  G05F1/595 ,  G05F1/46 ,  H01L29/78

Abstract: Some embodiments relate to a device disposed on a semiconductor substrate. The semiconductor substrate includes a base region and a crown structure extending upwardly from the base region. The crown structure is narrower than the base region. A plurality of fins extend upwardly from an upper surface of the crown structure. A gate dielectric material is disposed over upper surfaces and sidewalls of the plurality of the fins. A conductive electrode is disposed along sidewall portions of the gate dielectric material. An uppermost surface of the conductive electrode resides below the upper surfaces of the plurality of fins.

公开(公告)号：US10466731B2

公开(公告)日：2019-11-05

申请号：US15007684

申请日：2016-01-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yvonne Lin ,  Da-Wen Lin ,  Peter Huang ,  Paul Rousseau ,  Sheng-Jier Yang

IPC: G05F3/16 ,  G05F1/46 ,  G05F1/595 ,  H01L27/088 ,  H01L29/78 ,  G05F3/24 ,  H01L21/8234 ,  H01L29/06

Abstract: Some embodiments relate to a two transistor band gap reference circuit. A first transistor includes a first source, a first drain, a first body region separating the first source from the first drain, and a first gate. The first drain and first gate are coupled to a DC supply terminal. The second transistor includes a second source, a second drain, a second body region separating the second source from the second drain, and a second gate. The second gate is coupled to the DC supply terminal, and the second drain is coupled to the first source. Body bias circuitry is configured to apply a body bias voltage to at least one of the first and second body regions. Other embodiments relate to FinFET devices.

公开(公告)号：US20180356852A1

公开(公告)日：2018-12-13

申请号：US16106476

申请日：2018-08-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yvonne Lin ,  Da-Wen Lin ,  Peter Huang ,  Paul Rousseau ,  Sheng-Jier Yang

IPC: G05F3/16 ,  H01L29/78 ,  H01L29/06 ,  G05F1/595 ,  G05F1/46 ,  H01L21/8234 ,  H01L27/088

Abstract: Some embodiments relate to a method. A semiconductor substrate is provided and has a base region and a crown structure extending upwardly from the base region. A plurality of fins are formed to extend upwardly from an upper surface of the crown structure. A gate dielectric material is formed over upper surfaces and sidewalls of the plurality of the fins. A conductive electrode material is formed over upper surfaces and sidewalls of the gate dielectric material. An etch is performed to etch back the conductive electrode material so upper surfaces of etched back conductive electrodes reside below the upper surfaces of the plurality of fins.

公开(公告)号：US20170212545A1

公开(公告)日：2017-07-27

申请号：US15007684

申请日：2016-01-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yvonne Lin ,  Da-Wen Lin ,  Peter Huang ,  Paul Rousseau ,  Sheng-Jier Yang

IPC: G05F3/16 ,  H01L21/8234 ,  H01L29/06 ,  H01L27/088

CPC classification number: G05F3/16 ,  G05F1/465 ,  G05F1/468 ,  G05F1/595 ,  G05F3/247 ,  H01L21/823431 ,  H01L21/823475 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/0657 ,  H01L29/785

Abstract: Some embodiments relate to a two transistor band gap reference circuit. A first transistor includes a first source, a first drain, a first body region separating the first source from the first drain, and a first gate. The first drain and first gate are coupled to a DC supply terminal. The second transistor includes a second source, a second drain, a second body region separating the second source from the second drain, and a second gate. The second gate is coupled to the DC supply terminal, and the second drain is coupled to the first source. Body bias circuitry is configured to apply a body bias voltage to at least one of the first and second body regions. Other embodiments relate to FinFET devices.