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公开(公告)号：US20210255540A1
公开(公告)日：2021-08-19
申请号：US17306684
申请日：2021-05-03
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Peter Yu , Chih-Tung Hsu , Kevin Wang , Chih-Chia Hu , Roger Chen
Abstract: Examples of a multiple-mask multiple-exposure lithographic technique and suitable masks are provided herein. In some examples, a photomask includes a die area and a stitching region disposed adjacent to the die area and along a boundary of the photomask. The stitching region includes a mask feature for forming an integrated circuit feature and an alignment mark for in-chip overlay measurement.
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公开(公告)号：US20240377755A1
公开(公告)日：2024-11-14
申请号：US18780081
申请日：2024-07-22
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Peter Yu , Chih-Tung Hsu , Kevin Wang , Chih-Chia Hu , Roger Chen
Abstract: Examples of a multiple-mask multiple-exposure lithographic technique and suitable masks are provided herein. In some examples, a photomask includes a die area and a stitching region disposed adjacent to the die area and along a boundary of the photomask. The stitching region includes a mask feature for forming an integrated circuit feature and an alignment mark for in-chip overlay measurement.
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公开(公告)号：US12044977B2
公开(公告)日：2024-07-23
申请号：US18359447
申请日：2023-07-26
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Peter Yu , Chih-Tung Hsu , Kevin Wang , Chih-Chia Hu , Roger Chen
CPC classification number: G03F7/70475 , G03F1/38 , G03F1/42 , G03F1/70
Abstract: Examples of a multiple-mask multiple-exposure lithographic technique and suitable masks are provided herein. In some examples, a photomask includes a die area and a stitching region disposed adjacent to the die area and along a boundary of the photomask. The stitching region includes a mask feature for forming an integrated circuit feature and an alignment mark for in-chip overlay measurement.
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公开(公告)号：US20220357652A1
公开(公告)日：2022-11-10
申请号：US17874676
申请日：2022-07-27
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Peter Yu , Chih-Tung Hsu , Kevin Wang , Chih-Chia Hu , Roger Chen
Abstract: Examples of a multiple-mask multiple-exposure lithographic technique and suitable masks are provided herein. In some examples, a photomask includes a die area and a stitching region disposed adjacent to the die area and along a boundary of the photomask. The stitching region includes a mask feature for forming an integrated circuit feature and an alignment mark for in-chip overlay measurement.
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Patent Agency Ranking
公开(公告)号：US20200050102A1
公开(公告)日：2020-02-13
申请号：US16658909
申请日：2019-10-21
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Peter Yu , Chih-Tung Hsu , Kevin Wang , Chih-Chia Hu , Roger Chen
Abstract: Examples of a multiple-mask multiple-exposure lithographic technique and suitable masks are provided herein. In some examples, a photomask includes a die area and a stitching region disposed adjacent to the die area and along a boundary of the photomask. The stitching region includes a mask feature for forming an integrated circuit feature and an alignment mark for in-chip overlay measurement.
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公开(公告)号：US20230367229A1
公开(公告)日：2023-11-16
申请号：US18359447
申请日：2023-07-26
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Peter Yu , Chih-Tung Hsu , Kevin Wang , Chih-Chia Hu , Roger Chen
CPC classification number: G03F7/70475 , G03F1/38 , G03F1/42 , G03F1/70
Abstract: Examples of a multiple-mask multiple-exposure lithographic technique and suitable masks are provided herein. In some examples, a photomask includes a die area and a stitching region disposed adjacent to the die area and along a boundary of the photomask. The stitching region includes a mask feature for forming an integrated circuit feature and an alignment mark for in-chip overlay measurement.
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公开(公告)号：US11726408B2
公开(公告)日：2023-08-15
申请号：US17874676
申请日：2022-07-27
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Peter Yu , Chih-Tung Hsu , Kevin Wang , Chih-Chia Hu , Roger Chen
CPC classification number: G03F7/70475 , G03F1/38 , G03F1/42 , G03F1/70
Abstract: Examples of a multiple-mask multiple-exposure lithographic technique and suitable masks are provided herein. In some examples, a photomask includes a die area and a stitching region disposed adjacent to the die area and along a boundary of the photomask. The stitching region includes a mask feature for forming an integrated circuit feature and an alignment mark for in-chip overlay measurement.
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公开(公告)号：US10996558B2
公开(公告)日：2021-05-04
申请号：US16658909
申请日：2019-10-21
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Peter Yu , Chih-Tung Hsu , Kevin Wang , Chih-Chia Hu , Roger Chen
Abstract: Examples of a multiple-mask multiple-exposure lithographic technique and suitable masks are provided herein. In some examples, a photomask includes a die area and a stitching region disposed adjacent to the die area and along a boundary of the photomask. The stitching region includes a mask feature for forming an integrated circuit feature and an alignment mark for in-chip overlay measurement.
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公开(公告)号：US20190033706A1
公开(公告)日：2019-01-31
申请号：US15800140
申请日：2017-11-01
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Peter Yu , Chih-Tung Hsu , Kevin Wang , Chih-Chia Hu , Roger Chen
Abstract: Examples of a multiple-mask multiple-exposure lithographic technique and suitable masks are provided herein. In some examples, a photomask includes a die area and a stitching region disposed adjacent to the die area and along a boundary of the photomask. The stitching region includes a mask feature for forming an integrated circuit feature and an alignment mark for in-chip overlay measurement.
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