公开(公告)号：US12300639B2

公开(公告)日：2025-05-13

申请号：US17580942

申请日：2022-01-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Chia Hu ,  Ming-Fa Chen

IPC: H01L23/00 ,  H01L25/00 ,  H01L25/065

Abstract: Seamless bonding layers in semiconductor packages and methods of forming the same are disclosed. In an embodiment, a method includes forming a second passivation layer over a first metal pad and a second metal pad, the first metal pad and the second metal pad being disposed over a first passivation layer of a first semiconductor die; depositing a first bonding material over the second passivation layer to form a first portion of a first bonding layer, wherein at least a portion of a seam in the first bonding layer is between the first metal pad and the second metal pad; thinning the first portion of the first bonding layer to create a first opening from the seam; and re-depositing the first bonding material to fill the first opening and to form a second portion of the first bonding layer.

公开(公告)号：US20220367322A1

公开(公告)日：2022-11-17

申请号：US17815515

申请日：2022-07-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Chia Hu ,  Sen-Bor Jan ,  Hsien-Wei Chen ,  Ming-Fa Chen

IPC: H01L23/48 ,  H01L23/00 ,  H01L23/528 ,  H01L21/768 ,  H01L21/66

Abstract: A semiconductor device including a test pad contact and a method of manufacturing the semiconductor device are disclosed. In an embodiment, a semiconductor device may include a first metal feature and a second metal feature disposed in a single top metal layer over a substrate. A test pad may be formed over and electrically connected to the first metal feature. A first passivation layer may be formed over the second metal feature and the test pad and may cover top and side surfaces of the test pad. A first via may be formed penetrating the first passivation layer and contacting the test pad and a second via may be formed penetrating the first passivation layer and contacting the second metal feature.

公开(公告)号：US11335656B2

公开(公告)日：2022-05-17

申请号：US17027175

申请日：2020-09-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Chia Hu ,  Ching-Pin Yuan ,  Sung-Feng Yeh ,  Sen-Bor Jan ,  Ming-Fa Chen

IPC: H01L23/00 ,  H01L23/544 ,  H01L25/065 ,  H01L23/522

Abstract: A semiconductor device including a first die and a second die bonded to one another. The first die includes a first passivation layer over a substrate, and first bond pads in the first passivation layer. The second die includes a second passivation layer, which may be bonded to the first passivation layer, and second bond pads in the second passivation layer, which may be bonded to the first bond pads. The second bond pads include inner bond pads and outer bond pads. The outer bond pads may have a greater diameter than the inner bond pads as well as the first bond pads.

公开(公告)号：US20210118827A1

公开(公告)日：2021-04-22

申请号：US16655244

申请日：2019-10-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsien-Wei Chen ,  Ming-Fa Chen ,  Sen-Bor Jan ,  Chih-Chia Hu

IPC: H01L23/64 ,  H01L21/768 ,  H01L23/48 ,  H01L23/00

Abstract: A semiconductor package includes a first die and a second die. The first die includes a first spiral section and first bonding metallurgies of an inductor. The first bonding metallurgies are connected to the first spiral section. The second die is bonded to the first die. The second die includes a second spiral section and second bonding metallurgies of the inductor. The second bonding metallurgies are connected to the second spiral section. The inductor extends from the first die to the second die.

公开(公告)号：US20190033706A1

公开(公告)日：2019-01-31

申请号：US15800140

申请日：2017-11-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Peter Yu ,  Chih-Tung Hsu ,  Kevin Wang ,  Chih-Chia Hu ,  Roger Chen

IPC: G03F1/70 ,  G03F1/00 ,  G03F1/42

Abstract: Examples of a multiple-mask multiple-exposure lithographic technique and suitable masks are provided herein. In some examples, a photomask includes a die area and a stitching region disposed adjacent to the die area and along a boundary of the photomask. The stitching region includes a mask feature for forming an integrated circuit feature and an alignment mark for in-chip overlay measurement.

公开(公告)号：US20240377755A1

公开(公告)日：2024-11-14

申请号：US18780081

申请日：2024-07-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Peter Yu ,  Chih-Tung Hsu ,  Kevin Wang ,  Chih-Chia Hu ,  Roger Chen

IPC: G03F7/00 ,  G03F1/38 ,  G03F1/42 ,  G03F1/70

Abstract: Examples of a multiple-mask multiple-exposure lithographic technique and suitable masks are provided herein. In some examples, a photomask includes a die area and a stitching region disposed adjacent to the die area and along a boundary of the photomask. The stitching region includes a mask feature for forming an integrated circuit feature and an alignment mark for in-chip overlay measurement.

公开(公告)号：US12044977B2

公开(公告)日：2024-07-23

申请号：US18359447

申请日：2023-07-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Peter Yu ,  Chih-Tung Hsu ,  Kevin Wang ,  Chih-Chia Hu ,  Roger Chen

IPC: G03F7/20 ,  G03F1/38 ,  G03F1/42 ,  G03F1/70 ,  G03F7/00

CPC classification number: G03F7/70475 ,  G03F1/38 ,  G03F1/42 ,  G03F1/70

Abstract: Examples of a multiple-mask multiple-exposure lithographic technique and suitable masks are provided herein. In some examples, a photomask includes a die area and a stitching region disposed adjacent to the die area and along a boundary of the photomask. The stitching region includes a mask feature for forming an integrated circuit feature and an alignment mark for in-chip overlay measurement.

公开(公告)号：US20240153899A1

公开(公告)日：2024-05-09

申请号：US18411674

申请日：2024-01-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsien-Wei Chen ,  Ming-Fa Chen ,  Chih-Chia Hu

IPC: H01L23/00 ,  H01L23/495 ,  H01L23/498 ,  H03K19/1776

CPC classification number: H01L24/06 ,  H01L23/49503 ,  H01L23/49827 ,  H03K19/1776

Abstract: A method includes polishing a semiconductor substrate of a first die to reveal first through-vias that extend into the semiconductor substrate, forming a dielectric layer on the semiconductor substrate, and forming a plurality of bond pads in the dielectric layer. The plurality of bond pads include active bond pads and dummy bond pads. The active bond pads are electrically coupled to the first through-vias. The first die is bonded to a second die, and both of the active bond pads and the dummy bond pads are bonded to corresponding bond pads in the second die.

公开(公告)号：US20240021544A1

公开(公告)日：2024-01-18

申请号：US18358343

申请日：2023-07-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Chia Hu ,  Chun-Chiang Kuo ,  Sen-Bor Jan ,  Ming-Fa Chen ,  Hsien-Wei Chen

IPC: H01L23/58 ,  H01L23/522 ,  H01L23/532 ,  H01L29/06 ,  H01L23/00 ,  H01L25/00 ,  H01L25/065

CPC classification number: H01L23/585 ,  H01L23/5226 ,  H01L23/53295 ,  H01L29/0649 ,  H01L24/09 ,  H01L24/83 ,  H01L24/03 ,  H01L24/33 ,  H01L25/50 ,  H01L24/80 ,  H01L25/0657 ,  H01L23/562 ,  H01L2225/06568 ,  H01L2225/06565 ,  H01L2225/06593 ,  H01L2225/06513 ,  H01L2225/06524 ,  H01L2224/94

Abstract: A structure includes a first die and a second die. The first die includes a first bonding layer having a first plurality of bond pads disposed therein and a first seal ring disposed in the first bonding layer. The first bonding layer extends over the first seal ring. The second die includes a second bonding layer having a second plurality of bond pads disposed therein. The first plurality of bond pads is bonded to the second plurality of bond pads. The first bonding layer is bonded to the second bonding layer. An area interposed between the first seal ring and the second bonding layer is free of bond pads.

公开(公告)号：US11791243B2

公开(公告)日：2023-10-17

申请号：US17815515

申请日：2022-07-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Chia Hu ,  Sen-Bor Jan ,  Hsien-Wei Chen ,  Ming-Fa Chen

IPC: H01L23/48 ,  H01L23/528 ,  H01L21/768 ,  H01L21/66 ,  H01L23/00

CPC classification number: H01L23/481 ,  H01L21/76805 ,  H01L22/32 ,  H01L23/528 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/09 ,  H01L24/80 ,  H01L24/08 ,  H01L2224/03 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05186 ,  H01L2224/05647 ,  H01L2224/0603 ,  H01L2224/08146 ,  H01L2224/08235 ,  H01L2224/80447 ,  H01L2225/06513 ,  H01L2225/06524 ,  H01L2225/06596 ,  H01L2924/14 ,  H01L2224/05147 ,  H01L2924/013 ,  H01L2924/00014 ,  H01L2224/05124 ,  H01L2924/013 ,  H01L2924/00014 ,  H01L2224/05647 ,  H01L2924/013 ,  H01L2924/00014 ,  H01L2224/05166 ,  H01L2924/00014 ,  H01L2224/05186 ,  H01L2924/04941 ,  H01L2924/00014 ,  H01L2224/05181 ,  H01L2924/00014 ,  H01L2224/05186 ,  H01L2924/04953 ,  H01L2924/00014 ,  H01L2224/80447 ,  H01L2924/013 ,  H01L2924/00014 ,  H01L2224/05147 ,  H01L2924/00014

Abstract: A semiconductor device including a test pad contact and a method of manufacturing the semiconductor device are disclosed. In an embodiment, a semiconductor device may include a first metal feature and a second metal feature disposed in a single top metal layer over a substrate. A test pad may be formed over and electrically connected to the first metal feature. A first passivation layer may be formed over the second metal feature and the test pad and may cover top and side surfaces of the test pad. A first via may be formed penetrating the first passivation layer and contacting the test pad and a second via may be formed penetrating the first passivation layer and contacting the second metal feature.