公开(公告)号：US20150060873A1

公开(公告)日：2015-03-05

申请号：US14016302

申请日：2013-09-03

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Han-Chin Chiu ,  Trinh Hai Dang ,  Hsing-Lien Lin ,  Cheng-Yuan Tsai ,  Chia-Shiung Tsai ,  Xiaomeng Chen

IPC: H01L29/778 ,  H01L29/66

CPC classification number: H01L29/778 ,  H01L29/2003 ,  H01L29/66431 ,  H01L29/66462 ,  H01L29/7785 ,  H01L29/7787

Abstract: Some embodiments of the present disclosure relates to a crystalline passivation layer for effectively passivating III-N surfaces. Surface passivation of HEMTs reduces or eliminates the surface effects that can otherwise degrade device performance. The crystalline passivation layer reduces the degrading effects of surface traps and provides a good interface between a III-nitride surface and an insulator (e.g., gate dielectric formed over the passivation layer).

Abstract translation: 本公开的一些实施方案涉及用于有效钝化III-N表面的晶体钝化层。 HEMT的表面钝化减少或消除了否则会降低器件性能的表面效应。 结晶钝化层降低了表面陷阱的降解效应，并且在III族氮化物表面和绝缘体之间提供良好的界面（例如，在钝化层上形成的栅极电介质）。

公开(公告)号：US20160064664A1

公开(公告)日：2016-03-03

申请号：US14471101

申请日：2014-08-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Trinh Hai Dang ,  Hsing-Lien Lin ,  Chin-Wei Liang ,  Cheng-Yuan Tsai ,  Chia-Shiung Tsai

IPC: H01L45/00

CPC classification number: H01L45/146 ,  H01L45/08 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/1675

Abstract: An integrated circuit or semiconductor structure of a resistive random access memory (RRAM) cell is provided. The RRAM cell includes a bottom electrode and a data storage region having a variable resistance arranged over the bottom electrode. Further, the RRAM cell includes a diffusion barrier layer arranged over the data storage region, an ion reservoir region arranged over the diffusion barrier layer, and a top electrode arranged over the ion reservoir region. A method for manufacture the integrated circuit or semiconductor structure of the RRAM cell is also provided.

Abstract translation: 提供了电阻随机存取存储器（RRAM）单元的集成电路或半导体结构。 RRAM单元包括底部电极和布置在底部电极上的具有可变电阻的数据存储区域。 此外，RRAM单元包括布置在数据存储区域上的扩散阻挡层，布置在扩散阻挡层上的离子储存区域和布置在离子储存区域上的顶部电极。 还提供了一种用于制造RRAM单元的集成电路或半导体结构的方法。

公开(公告)号：US10170699B2

公开(公告)日：2019-01-01

申请号：US15433353

申请日：2017-02-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Trinh Hai Dang ,  Hsing-Lien Lin ,  Kai-Wen Cheng ,  Cheng-Yuan Tsai ,  Chia-Shiung Tsai ,  Ru-Liang Lee

IPC: H01L27/24 ,  H01L45/00

Abstract: The present disclosure relates to a method of forming a resistive random access memory (RRAM) cell having a reduced leakage current, and an associated apparatus. In some embodiments, the method is performed by forming a bottom electrode layer over a lower metal interconnect layer. A dielectric data storage layer having a variable resistance is formed onto the bottom electrode layer in-situ with forming at least a part of the bottom electrode layer. A top electrode layer is formed over the dielectric data storage layer. By forming the dielectric data storage layer in-situ with forming at least a part of the bottom electrode layer, leakage current, leakage current distribution and device yield of the RRAM cell are improved.

公开(公告)号：US09431609B2

公开(公告)日：2016-08-30

申请号：US14459361

申请日：2014-08-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Trinh Hai Dang ,  Hsing-Lien Lin ,  Cheng-Yuan Tsai ,  Chia-Shiung Tsai ,  Ru-Liang Lee

IPC: H01L21/00 ,  H01L45/00

CPC classification number: H01L45/1616 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/146 ,  H01L45/147 ,  H01L45/1675

Abstract: The present disclosure relates to a method of forming an RRAM cell having a dielectric data layer that provides good performance, device yield, and data retention, and an associated apparatus. In some embodiments, the method is performed by forming an RRAM film stack having a bottom electrode layer disposed over a semiconductor substrate, a top electrode layer, and a dielectric data storage layer disposed between the bottom electrode and the top electrode. The dielectric data storage layer has a performance enhancing layer with a hydrogen-doped oxide and a data retention layer having an aluminum oxide. The RRAM film stack is then patterned according to one or more masking layers to form a top electrode and a bottom electrode, and an upper metal interconnect layer is formed at a position electrically contacting the top electrode.

Abstract translation: 本公开涉及一种形成具有提供良好性能，设备产量和数据保持的介质数据层的RRAM单元的方法以及相关联的设备。 在一些实施例中，通过形成具有设置在半导体衬底上的底部电极层，顶部电极层和设置在底部电极和顶部电极之间的电介质数据存储层的RRAM膜堆栈来执行该方法。 电介质数据存储层具有具有氢掺杂氧化物的性能增强层和具有氧化铝的数据保留层。 然后根据一个或多个掩模层对RRAM膜堆叠进行构图以形成顶部电极和底部电极，并且在与顶部电极电接触的位置处形成上部金属互连层。

公开(公告)号：US10388865B2

公开(公告)日：2019-08-20

申请号：US15871559

申请日：2018-01-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Trinh Hai Dang ,  Hsing-Lien Lin ,  Cheng-Yuan Tsai ,  Chin-Chieh Yang ,  Yu-Wen Liao ,  Wen-Ting Chu ,  Chia-Shiung Tsai

IPC: H01L21/8239 ,  H01L45/00

Abstract: The present disclosure, in some embodiments, relates to a resistive random access memory (RRAM) cell. The RRAM cell has a bottom electrode disposed over a lower interconnect layer and a data storage layer having a first thickness over the bottom electrode. A capping layer is disposed over the data storage layer. The capping layer has a second thickness that is in a range of between approximately 2 and approximately 3 times thicker than the first thickness. A top electrode is disposed over the capping layer and an upper interconnect layer is disposed over the top electrode.

公开(公告)号：US09876167B2

公开(公告)日：2018-01-23

申请号：US14592340

申请日：2015-01-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Trinh Hai Dang ,  Hsing-Lien Lin ,  Cheng-Yuan Tsai ,  Chin-Chieh Yang ,  Yu-Wen Liao ,  Wen-Ting Chu ,  Chia-Shiung Tsai

IPC: H05B3/00 ,  H01L45/00

CPC classification number: H01L45/1233 ,  H01L45/08 ,  H01L45/12 ,  H01L45/146 ,  H01L45/1616 ,  H01L45/1641 ,  H01L45/1675

Abstract: The present disclosure relates to a method of forming a resistive random access memory (RRAM) cell having a good yield, and an associated apparatus. In some embodiments, the method is performed by forming a bottom electrode over a lower metal interconnect layer, and forming a variable resistance dielectric data storage layer having a first thickness onto the bottom electrode. A capping layer is formed onto the dielectric data storage layer. The capping layer has a second thickness that is in a range of between approximately 2 to approximately 3 times thicker than the first thickness. A top electrode is formed over the capping layer, and an upper metal interconnect layer is formed over the top electrode.

公开(公告)号：US09130026B2

公开(公告)日：2015-09-08

申请号：US14016302

申请日：2013-09-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Han-Chin Chiu ,  Trinh Hai Dang ,  Hsing-Lien Lin ,  Cheng-Yuan Tsai ,  Chia-Shiung Tsai ,  Xiaomeng Chen

IPC: H01L29/778 ,  H01L29/66

CPC classification number: H01L29/778 ,  H01L29/2003 ,  H01L29/66431 ,  H01L29/66462 ,  H01L29/7785 ,  H01L29/7787

Abstract: Some embodiments of the present disclosure relates to a crystalline passivation layer for effectively passivating III-N surfaces. Surface passivation of HEMTs reduces or eliminates the surface effects that can otherwise degrade device performance. The crystalline passivation layer reduces the degrading effects of surface traps and provides a good interface between a III-nitride surface and an insulator (e.g., gate dielectric formed over the passivation layer).

Abstract translation: 本公开的一些实施方案涉及用于有效钝化III-N表面的晶体钝化层。 HEMT的表面钝化减少或消除了否则会降低器件性能的表面效应。 结晶钝化层降低了表面陷阱的降解效应，并且在III族氮化物表面和绝缘体之间提供良好的界面（例如，在钝化层上形成的栅极电介质）。

公开(公告)号：US11637239B2

公开(公告)日：2023-04-25

申请号：US16540130

申请日：2019-08-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Trinh Hai Dang ,  Hsing-Lien Lin ,  Cheng-Yuan Tsai ,  Chin-Chieh Yang ,  Yu-Wen Liao ,  Wen-Ting Chu ,  Chia-Shiung Tsai

IPC: H01L45/00

Abstract: The present disclosure, in some embodiments, relates to a resistive random access memory (RRAM) cell. The RRAM cell has a bottom electrode over a substrate. A data storage layer is over the bottom electrode and has a first thickness. A capping layer is over the data storage layer. The capping layer has a second thickness that is in a range of between approximately 1.9 and approximately 3 times thicker than the first thickness. A top electrode is over the capping layer.

公开(公告)号：US10193065B2

公开(公告)日：2019-01-29

申请号：US14471101

申请日：2014-08-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Trinh Hai Dang ,  Hsing-Lien Lin ,  Chin-Wei Liang ,  Cheng-Yuan Tsai ,  Chia-Shiung Tsai

IPC: H01L45/00

Abstract: An integrated circuit or semiconductor structure of a resistive random access memory (RRAM) cell is provided. The RRAM cell includes a bottom electrode and a data storage region having a variable resistance arranged over the bottom electrode. Further, the RRAM cell includes a diffusion barrier layer arranged over the data storage region, an ion reservoir region arranged over the diffusion barrier layer, and a top electrode arranged over the ion reservoir region. A method for manufacture the integrated circuit or semiconductor structure of the RRAM cell is also provided.

公开(公告)号：US20180138402A1

公开(公告)日：2018-05-17

申请号：US15871559

申请日：2018-01-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Trinh Hai Dang ,  Hsing-Lien Lin ,  Cheng-Yuan Tsai ,  Chin-Chieh Yang ,  Yu-Wen Liao ,  Wen-Ting Chu ,  Chia-Shiung Tsai

IPC: H01L45/00

CPC classification number: H01L45/1233 ,  H01L45/08 ,  H01L45/12 ,  H01L45/146 ,  H01L45/1616 ,  H01L45/1641 ,  H01L45/1675

Abstract: The present disclosure, in some embodiments, relates to a resistive random access memory (RRAM) cell. The RRAM cell has a bottom electrode disposed over a lower interconnect layer and a data storage layer having a first thickness over the bottom electrode. A capping layer is disposed over the data storage layer. The capping layer has a second thickness that is in a range of between approximately 2 and approximately 3 times thicker than the first thickness. A top electrode is disposed over the capping layer and an upper interconnect layer is disposed over the top electrode.