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公开(公告)号：US12035537B2
公开(公告)日：2024-07-09
申请号：US17373886
申请日：2021-07-13
发明人： Bi-Shen Lee , Yi Yang Wei , Hai-Dang Trinh , Hsun-Chung Kuang , Cheng-Yuan Tsai
摘要： In some embodiments, the present disclosure relates to a method of forming an integrated chip. The method includes forming a lower electrode layer over a substrate, and an un-patterned amorphous initiation layer over the lower electrode layer. An intermediate ferroelectric material layer is formed have a substantially uniform amorphous phase on the un-patterned amorphous initiation layer. An anneal process is performed to change the intermediate ferroelectric material layer to a ferroelectric material layer having a substantially uniform orthorhombic crystalline phase. An upper electrode layer is formed over the ferroelectric material layer. One or more patterning processes are performed on the upper electrode layer, the ferroelectric material layer, the un-patterned amorphous initiation layer, and the lower electrode layer to form a ferroelectric memory device. An upper ILD layer is formed over the ferroelectric memory device, and an upper interconnect is formed to contact the ferroelectric memory device.
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公开(公告)号：US20240064998A1
公开(公告)日：2024-02-22
申请号：US18386649
申请日：2023-11-03
发明人： Bi-Shen Lee , Yi Yang Wei , Hsing-Lien Lin , Hsun-Chung Kuang , Cheng-Yuan Tsai , Hai-Dang Trinh
IPC分类号： H10B53/30
摘要： A method includes forming a bottom electrode layer, and depositing a first ferroelectric layer over the bottom electrode layer. The first ferroelectric layer is amorphous. A second ferroelectric layer is deposited over the first ferroelectric layer, and the second ferroelectric layer has a polycrystalline structure. The method further includes depositing a third ferroelectric layer over the second ferroelectric layer, with the third ferroelectric layer being amorphous, depositing a top electrode layer over the third ferroelectric layer, and patterning the top electrode layer, the third ferroelectric layer, the second ferroelectric layer, the first ferroelectric layer, and the bottom electrode layer to form a Ferroelectric Random Access Memory cell.
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公开(公告)号：US20220392906A1
公开(公告)日：2022-12-08
申请号：US17818649
申请日：2022-08-09
发明人： Bi-Shen Lee , Yi Yang Wei , Hsing-Lien Lin , Hsun-Chung Kuang , Cheng-Yuan Tsai , Hai-Dang Trinh
IPC分类号： H01L27/11507 , H01L49/02
摘要： A method includes forming a bottom electrode layer, and depositing a first ferroelectric layer over the bottom electrode layer. The first ferroelectric layer is amorphous. A second ferroelectric layer is deposited over the first ferroelectric layer, and the second ferroelectric layer has a polycrystalline structure. The method further includes depositing a third ferroelectric layer over the second ferroelectric layer, with the third ferroelectric layer being amorphous, depositing a top electrode layer over the third ferroelectric layer, and patterning the top electrode layer, the third ferroelectric layer, the second ferroelectric layer, the first ferroelectric layer, and the bottom electrode layer to form a Ferroelectric Random Access Memory cell.
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公开(公告)号：US11522066B2
公开(公告)日：2022-12-06
申请号：US17114715
申请日：2020-12-08
发明人： Han-Chin Chiu , Chi-Ming Chen , Cheng-Yuan Tsai , Fu-Wei Yao
IPC分类号： H01L29/66 , H01L29/778 , H01L29/205 , H01L21/02 , H01L23/29 , H01L29/20 , H01L23/31 , H01L29/78 , H01L29/10
摘要： Some embodiments of the present disclosure relate to a high electron mobility transistor (HEMT) which includes a heterojunction structure arranged over a semiconductor substrate. The heterojunction structure includes a binary III/V semiconductor layer is a first III-nitride material and a ternary III/V semiconductor layer arranged over the binary III/V semiconductor layer and is a second III-nitride material. Source and drain regions are arranged over the ternary III/V semiconductor layer. A gate structure is arranged over the heterojunction structure and arranged between the source and drain regions. The gate structure is a third III-nitride material. A first passivation layer directly contacts an entire sidewall surface of the gate structure and is a fourth III-nitride material. The entire sidewall surface has no dangling bond. A second passivation layer is conformally disposed along the first passivation layer, the second passivation layer has no physical contact with the gate structure.
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公开(公告)号：US20220310635A1
公开(公告)日：2022-09-29
申请号：US17346627
申请日：2021-06-14
发明人： Hai-Dang Trinh , Yi Yang Wei , Bi-Shen Lee , Fa-Shen Jiang , Hsun-Chung Kuang , Cheng-Yuan Tsai
IPC分类号： H01L27/11507 , H01L49/02
摘要： In some embodiments, the present disclosure relates to an integrated chip that includes one or more interconnect dielectric layers arranged over a substrate. A bottom electrode is disposed over a conductive structure and extends through the one or more interconnect dielectric layers. A top electrode is disposed over the bottom electrode. A ferroelectric layer is disposed between and contacts the bottom electrode and the top electrode. The ferroelectric layer includes a first lower horizontal portion, a first upper horizontal portion arranged above the first lower horizontal portion, and a first sidewall portion and coupling the first lower horizontal portion to the first upper horizontal portion.
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公开(公告)号：US20220223634A1
公开(公告)日：2022-07-14
申请号：US17144757
申请日：2021-01-08
发明人： Che Wei Yang , Sheng-Chan Li , Tsun-Kai Tsao , Chih-Cheng Shih , Sheng-Chau Chen , Cheng-Yuan Tsai
IPC分类号： H01L27/146
摘要： In some embodiments, the present disclosure relates to an integrated chip that includes a first image sensing element and a second image sensing element arranged over a substrate. A first micro-lens is arranged over the first image sensing element, and a second micro-lens is arranged over the second image sensing element. A composite deep trench isolation structure is arranged between the first and second image sensing elements. The composite deep trench isolation structure includes a lower portion arranged over the substrate and an upper portion arranged over the lower portion. The lower portion includes a first material, and the upper portion includes a second material that has a higher reflectivity than the first material.
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公开(公告)号：US11367623B2
公开(公告)日：2022-06-21
申请号：US17070461
申请日：2020-10-14
IPC分类号： H01L45/00 , H01L21/311 , H01L21/3105 , H01L43/02 , H01L23/528 , H01L43/08 , H01L43/12
摘要： A method of forming a memory device is provided. In some embodiments, a memory cell is formed over a substrate, and a sidewall spacer layer is formed along the memory cell. A lower etch stop layer is formed on the sidewall spacer layer, and an upper dielectric layer is formed on the lower etch stop layer. A first etching process is performed to etch back the upper dielectric layer using the lower etch stop layer as an etch endpoint.
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公开(公告)号：US11183627B2
公开(公告)日：2021-11-23
申请号：US16732385
申请日：2020-01-02
摘要： Some embodiments relate to a memory device. The memory device includes a memory cell overlying a substrate, the memory cell includes a data storage structure disposed between a lower electrode and an upper electrode. An upper interconnect wire overlying the upper electrode. A first inter-level dielectric (ILD) layer surrounding the memory cell and the upper interconnect wire. A second ILD layer overlying the first ILD layer and surrounding the upper interconnect wire. A sidewall spacer laterally surrounding the memory cell. The sidewall spacer has a first sidewall abutting the first ILD layer and a second sidewall abutting the second ILD layer.
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公开(公告)号：US11165021B2
公开(公告)日：2021-11-02
申请号：US16601771
申请日：2019-10-15
发明人： Fa-Shen Jiang , Cheng-Yuan Tsai , Hai-Dang Trinh , Hsing-Lien Lin , Bi-Shen Lee
摘要： The present disclosure relates to a method of forming a resistive random access memory (RRAM) device. In some embodiments, the method may be performed by forming a first electrode structure over a substrate. A doped data storage element is formed over the first electrode structure. The doped data storage element is formed by forming a first data storage layer over the first electrode structure and forming a second data storage layer over the first data storage layer. The first data storage layer is formed to have a first doping concentration of a dopant and the second data storage layer is formed to have a second doping concentration of the dopant that is less than the first doping concentration. A second electrode structure is formed over the doped data storage element.
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公开(公告)号：US11038010B2
公开(公告)日：2021-06-15
申请号：US14609159
申请日：2015-01-29
摘要： A structure includes a semiconductor substrate, a conductor-insulator-conductor capacitor. The conductor-insulator-conductor capacitor is disposed on the semiconductor substrate and includes a first conductor, a nitrogenous dielectric layer and a second conductor. The nitrogenous dielectric layer is disposed on the first conductor and the second conductor is disposed on the nitrogenous dielectric layer.
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