-
公开(公告)号：US11631810B2
公开(公告)日：2023-04-18
申请号：US17233755
申请日：2021-04-19
发明人： Chao-Yang Chen , Chun-Yang Tsai , Kuo-Ching Huang , Wen-Ting Chu , Pili Huang , Cheng-Jun Wu
IPC分类号： H01L27/088 , H01L21/8236 , H01L45/00 , H01L27/24
摘要： In some embodiments, the present disclosure relates to an integrated chip. The integrated chip includes one or more lower interconnects arranged within a dielectric structure over a substrate. A bottom electrode is disposed over one of the one or more lower interconnects. The bottom electrode includes a first material having a first electronegativity. A data storage layer separates the bottom electrode from a top electrode. The bottom electrode is between the data storage layer and the substrate. A reactivity reducing layer includes a second material and has a second electronegativity that is greater than or equal to the first electronegativity. The second material contacts a lower surface of the bottom electrode that faces the substrate.
-
公开(公告)号：US11611038B2
公开(公告)日：2023-03-21
申请号：US17171278
申请日：2021-02-09
发明人： Fu-Chen Chang , Kuo-Chi Tu , Wen-Ting Chu , Chu-Jie Huang
摘要： Various embodiments of the present application are directed towards a resistive random-access memory (RRAM) cell comprising a barrier layer to constrain the movement of metal cations during operation of the RRAM cell. In some embodiments, the RRAM cell further comprises a bottom electrode, a top electrode, a switching layer, and an active metal layer. The switching layer, the barrier layer, and the active metal layer are stacked between the bottom and top electrodes, and the barrier layer is between the switching and active metal layers. The barrier layer is conductive and between has a lattice constant less than that of the active metal layer.
-
公开(公告)号：US11296147B2
公开(公告)日：2022-04-05
申请号：US16413716
申请日：2019-05-16
发明人： Chieh-Fei Chiu , Yong-Shiuan Tsair , Wen-Ting Chu , Yu-Wen Liao , Chin-Yu Mei , Po-Hao Tseng
摘要： A memory device includes a first bottom electrode, a first memory stack, and a second memory stack. The first bottom electrode has a first portion and a second portion connected to the first portion. The first memory stack is over the first portion of the first bottom electrode. The first memory stack includes a first resistive switching element and a first top electrode over the first resistive switching element. The second memory stack is over the second portion of the first bottom electrode. The second memory stack comprises a second resistive switching element and a second top electrode over the second resistive switching element.
-
公开(公告)号：US11276819B2
公开(公告)日：2022-03-15
申请号：US16587218
申请日：2019-09-30
发明人： Chih-Yang Chang , Wen-Ting Chu
摘要： Some embodiments relate to an integrated circuit including one or more memory cells arranged over a semiconductor substrate between an upper metal interconnect layer and a lower metal interconnect layer. A memory cell includes a bottom electrode disposed over the lower metal interconnect layer, a data storage or dielectric layer disposed over the bottom electrode, and a top electrode disposed over the data storage or dielectric layer. An upper surface of the top electrode is in direct contact with the upper metal interconnect layer without a via or contact coupling the upper surface of the top electrode to the upper metal interconnect layer. Sidewall spacers are arranged along sidewalls of the top electrode, and have bottom surfaces that rest on an upper surface of the data storage or dielectric layer.
-
公开(公告)号：US11201281B2
公开(公告)日：2021-12-14
申请号：US16939583
申请日：2020-07-27
发明人： Hsia-Wei Chen , Chih-Yang Chang , Chin-Chieh Yang , Jen-Sheng Yang , Sheng-Hung Shih , Tung-Sheng Hsiao , Wen-Ting Chu , Yu-Wen Liao , I-Ching Chen
IPC分类号： H01L43/02 , H01L23/538 , H01L43/12 , H01L27/22 , H01L45/00 , H01L21/768 , H01L27/24 , H01L43/08
摘要： Various embodiments of the present application are directed towards a method for forming a flat via top surface for memory, as well as an integrated circuit (IC) resulting from the method. In some embodiments, an etch is performed into a dielectric layer to form an opening. A liner layer is formed covering the dielectric layer and lining the opening. A lower body layer is formed covering the dielectric layer and filling a remainder of the opening over the liner layer. A top surface of the lower body layer and a top surface of the liner layer are recessed to below a top surface of the dielectric layer to partially clear the opening. A homogeneous upper body layer is formed covering the dielectric layer and partially filling the opening. A planarization is performed into the homogeneous upper body layer until the dielectric layer is reached.
-
公开(公告)号：US11107982B2
公开(公告)日：2021-08-31
申请号：US16601800
申请日：2019-10-15
发明人： Chieh-Fei Chiu , Wen-Ting Chu , Yong-Shiuan Tsair , Yu-Wen Liao , Chin-Yu Mei , Po-Hao Tseng
IPC分类号： H01L45/00 , H01L23/31 , H01L23/495 , H01L23/48
摘要： The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a lower inter-level dielectric (ILD) structure surrounding a plurality of lower interconnect layers over a substrate. An etch stop material is disposed over the lower ILD structure. A bottom electrode is arranged over an upper surface of the etch stop material, a data storage structure is disposed on an upper surface of the bottom electrode and is configured to store a data state, and a top electrode is disposed on an upper surface of the data storage structure. A first interconnect via contacts the upper surface the bottom electrode and a second interconnect via contacts the top electrode.
-
公开(公告)号：US11094744B2
公开(公告)日：2021-08-17
申请号：US16695537
申请日：2019-11-26
发明人： Hsia-Wei Chen , Chih-Yang Chang , Chin-Chieh Yang , Jen-Sheng Yang , Kuo-Chi Tu , Wen-Ting Chu , Yu-Wen Liao
IPC分类号： H01L27/105 , H01L23/522 , H01L23/528 , H01L27/24 , H01L45/00 , H01L27/102
摘要： The present disclosure, in some embodiments, relates to a method of forming an integrated chip. The method may be performed by forming a memory device over a substrate and forming an inter-level dielectric (ILD) layer over the memory device. The ILD layer is selectively etched to define a first cavity that exposes a top of the memory device and to define a second cavity that is laterally separated from the first cavity by the ILD layer. The second cavity is defined by a smooth sidewall of the ILD layer that extends between upper and lower surfaces of the ILD layer. A conductive material is formed within the first cavity and the second cavity.
-
公开(公告)号：US11038108B2
公开(公告)日：2021-06-15
申请号：US16422207
申请日：2019-05-24
发明人： Wei-Ming Wang , Chia-Wei Liu , Jen-Sheng Yang , Wen-Ting Chu , Yu-Wen Liao , Huei-Tzu Wang
摘要： The present disclosure is directed to a method for the formation of resistive random-access memory (RRAM) structures with a low profile between or within metallization layers. For example, the method includes forming, on a substrate, a first metallization layer with conductive structures and a first dielectric layer abutting sidewall surfaces of the conductive structures; etching a portion of the first dielectric layer to expose a portion of the sidewall surfaces of the conductive structures; depositing a memory stack on the first metallization layer, the exposed portion of the sidewall surfaces, and a top surface of the conductive structures; patterning the memory stack to form a memory structure that covers the exposed portion of the sidewall surfaces and the top surface of the conductive structures; depositing a second dielectric layer to encapsulate the memory stack; and forming a second metallization layer on the second dielectric layer.
-
公开(公告)号：US11037990B2
公开(公告)日：2021-06-15
申请号：US16887232
申请日：2020-05-29
发明人： Hsia-Wei Chen , Wen-Ting Chu , Yu-Wen Liao
摘要： Various embodiments of the present application are directed towards an integrated chip comprising memory cells separated by a void-free dielectric structure. In some embodiments, a pair of memory cell structures is formed on a via dielectric layer, where the memory cell structures are separated by an inter-cell area. An inter-cell filler layer is formed covering the memory cell structures and the via dielectric layer, and further filling the inter-cell area. The inter-cell filler layer is recessed until a top surface of the inter-cell filler layer is below a top surface of the pair of memory cell structures and the inter-cell area is partially cleared. An interconnect dielectric layer is formed covering the memory cell structures and the inter-cell filler layer, and further filling a cleared portion of the inter-cell area.
-
公开(公告)号：US11037941B2
公开(公告)日：2021-06-15
申请号：US16558750
申请日：2019-09-03
发明人： Tzu-Yu Chen , Kuo-Chi Tu , Wen-Ting Chu , Yong-Shiuan Tsair
IPC分类号： H01L27/11507 , H01L27/11509 , H01L21/311 , H01L29/66 , H01L21/762 , H01L29/78 , H01L29/06 , H01L21/266 , H01L21/321 , H01L29/51 , H01L21/3105 , H01L29/08 , H01L21/265
摘要： A method for forming an integrated circuit (IC) and an IC are disclosed. The method for forming the IC includes: forming an isolation structure separating a memory semiconductor region from a logic semiconductor region; forming a memory cell structure on the memory semiconductor region; forming a memory capping layer covering the memory cell structure and the logic semiconductor region; performing a first etch into the memory capping layer to remove the memory capping layer from the logic semiconductor region, and to define a slanted, logic-facing sidewall on the isolation structure; forming a logic device structure on the logic semiconductor region; and performing a second etch into the memory capping layer to remove the memory capping layer from the memory semiconductor, while leaving a dummy segment of the memory capping layer that defines the logic-facing sidewall.
-
-
-
-
-
-
-
-
-
搜索结果
165 条记录 (耗时 0.024 秒)